linux/mfd/stm32-timers.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copyright (C) STMicroelectronics 2016
0004  * Author: Benjamin Gaignard <benjamin.gaignard@st.com>
0005  */
0006
0007 #ifndef _LINUX_STM32_GPTIMER_H_
0008 #define _LINUX_STM32_GPTIMER_H_
0009
0010 #include <linux/clk.h>
0011 #include <linux/dmaengine.h>
0012 #include <linux/dma-mapping.h>
0013 #include <linux/regmap.h>
0014
0015 #define TIM_CR1     0x00    /* Control Register 1      */
0016 #define TIM_CR2     0x04    /* Control Register 2      */
0017 #define TIM_SMCR    0x08    /* Slave mode control reg  */
0018 #define TIM_DIER    0x0C    /* DMA/interrupt register  */
0019 #define TIM_SR      0x10    /* Status register     */
0020 #define TIM_EGR     0x14    /* Event Generation Reg    */
0021 #define TIM_CCMR1   0x18    /* Capt/Comp 1 Mode Reg    */
0022 #define TIM_CCMR2   0x1C    /* Capt/Comp 2 Mode Reg    */
0023 #define TIM_CCER    0x20    /* Capt/Comp Enable Reg    */
0024 #define TIM_CNT     0x24    /* Counter         */
0025 #define TIM_PSC     0x28    /* Prescaler               */
0026 #define TIM_ARR     0x2c    /* Auto-Reload Register    */
0027 #define TIM_CCR1    0x34    /* Capt/Comp Register 1    */
0028 #define TIM_CCR2    0x38    /* Capt/Comp Register 2    */
0029 #define TIM_CCR3    0x3C    /* Capt/Comp Register 3    */
0030 #define TIM_CCR4    0x40    /* Capt/Comp Register 4    */
0031 #define TIM_BDTR    0x44    /* Break and Dead-Time Reg */
0032 #define TIM_DCR     0x48    /* DMA control register    */
0033 #define TIM_DMAR    0x4C    /* DMA register for transfer */
0034
0035 #define TIM_CR1_CEN BIT(0)  /* Counter Enable      */
0036 #define TIM_CR1_DIR BIT(4)  /* Counter Direction       */
0037 #define TIM_CR1_ARPE    BIT(7)  /* Auto-reload Preload Ena */
0038 #define TIM_CR2_MMS (BIT(4) | BIT(5) | BIT(6)) /* Master mode selection */
0039 #define TIM_CR2_MMS2    GENMASK(23, 20) /* Master mode selection 2 */
0040 #define TIM_SMCR_SMS    (BIT(0) | BIT(1) | BIT(2)) /* Slave mode selection */
0041 #define TIM_SMCR_TS (BIT(4) | BIT(5) | BIT(6)) /* Trigger selection */
0042 #define TIM_DIER_UIE    BIT(0)  /* Update interrupt    */
0043 #define TIM_DIER_UDE    BIT(8)  /* Update DMA request Enable */
0044 #define TIM_DIER_CC1DE  BIT(9)  /* CC1 DMA request Enable  */
0045 #define TIM_DIER_CC2DE  BIT(10) /* CC2 DMA request Enable  */
0046 #define TIM_DIER_CC3DE  BIT(11) /* CC3 DMA request Enable  */
0047 #define TIM_DIER_CC4DE  BIT(12) /* CC4 DMA request Enable  */
0048 #define TIM_DIER_COMDE  BIT(13) /* COM DMA request Enable  */
0049 #define TIM_DIER_TDE    BIT(14) /* Trigger DMA request Enable */
0050 #define TIM_SR_UIF  BIT(0)  /* Update interrupt flag   */
0051 #define TIM_EGR_UG  BIT(0)  /* Update Generation       */
0052 #define TIM_CCMR_PE BIT(3)  /* Channel Preload Enable  */
0053 #define TIM_CCMR_M1 (BIT(6) | BIT(5))  /* Channel PWM Mode 1 */
0054 #define TIM_CCMR_CC1S       (BIT(0) | BIT(1)) /* Capture/compare 1 sel */
0055 #define TIM_CCMR_IC1PSC     GENMASK(3, 2)   /* Input capture 1 prescaler */
0056 #define TIM_CCMR_CC2S       (BIT(8) | BIT(9)) /* Capture/compare 2 sel */
0057 #define TIM_CCMR_IC2PSC     GENMASK(11, 10) /* Input capture 2 prescaler */
0058 #define TIM_CCMR_CC1S_TI1   BIT(0)  /* IC1/IC3 selects TI1/TI3 */
0059 #define TIM_CCMR_CC1S_TI2   BIT(1)  /* IC1/IC3 selects TI2/TI4 */
0060 #define TIM_CCMR_CC2S_TI2   BIT(8)  /* IC2/IC4 selects TI2/TI4 */
0061 #define TIM_CCMR_CC2S_TI1   BIT(9)  /* IC2/IC4 selects TI1/TI3 */
0062 #define TIM_CCER_CC1E   BIT(0)  /* Capt/Comp 1  out Ena    */
0063 #define TIM_CCER_CC1P   BIT(1)  /* Capt/Comp 1  Polarity   */
0064 #define TIM_CCER_CC1NE  BIT(2)  /* Capt/Comp 1N out Ena    */
0065 #define TIM_CCER_CC1NP  BIT(3)  /* Capt/Comp 1N Polarity   */
0066 #define TIM_CCER_CC2E   BIT(4)  /* Capt/Comp 2  out Ena    */
0067 #define TIM_CCER_CC2P   BIT(5)  /* Capt/Comp 2  Polarity   */
0068 #define TIM_CCER_CC3E   BIT(8)  /* Capt/Comp 3  out Ena    */
0069 #define TIM_CCER_CC3P   BIT(9)  /* Capt/Comp 3  Polarity   */
0070 #define TIM_CCER_CC4E   BIT(12) /* Capt/Comp 4  out Ena    */
0071 #define TIM_CCER_CC4P   BIT(13) /* Capt/Comp 4  Polarity   */
0072 #define TIM_CCER_CCXE   (BIT(0) | BIT(4) | BIT(8) | BIT(12))
0073 #define TIM_BDTR_BKE(x) BIT(12 + (x) * 12) /* Break input enable */
0074 #define TIM_BDTR_BKP(x) BIT(13 + (x) * 12) /* Break input polarity */
0075 #define TIM_BDTR_AOE    BIT(14) /* Automatic Output Enable */
0076 #define TIM_BDTR_MOE    BIT(15) /* Main Output Enable      */
0077 #define TIM_BDTR_BKF(x) (0xf << (16 + (x) * 4))
0078 #define TIM_DCR_DBA GENMASK(4, 0)   /* DMA base addr */
0079 #define TIM_DCR_DBL GENMASK(12, 8)  /* DMA burst len */
0080
0081 #define MAX_TIM_PSC     0xFFFF
0082 #define MAX_TIM_ICPSC       0x3
0083 #define TIM_CR2_MMS_SHIFT   4
0084 #define TIM_CR2_MMS2_SHIFT  20
0085 #define TIM_SMCR_SMS_SLAVE_MODE_DISABLED    0 /* counts on internal clock when CEN=1 */
0086 #define TIM_SMCR_SMS_ENCODER_MODE_1     1 /* counts TI1FP1 edges, depending on TI2FP2 level */
0087 #define TIM_SMCR_SMS_ENCODER_MODE_2     2 /* counts TI2FP2 edges, depending on TI1FP1 level */
0088 #define TIM_SMCR_SMS_ENCODER_MODE_3     3 /* counts on both TI1FP1 and TI2FP2 edges */
0089 #define TIM_SMCR_TS_SHIFT   4
0090 #define TIM_BDTR_BKF_MASK   0xF
0091 #define TIM_BDTR_BKF_SHIFT(x)   (16 + (x) * 4)
0092
0093 enum stm32_timers_dmas {
0094     STM32_TIMERS_DMA_CH1,
0095     STM32_TIMERS_DMA_CH2,
0096     STM32_TIMERS_DMA_CH3,
0097     STM32_TIMERS_DMA_CH4,
0098     STM32_TIMERS_DMA_UP,
0099     STM32_TIMERS_DMA_TRIG,
0100     STM32_TIMERS_DMA_COM,
0101     STM32_TIMERS_MAX_DMAS,
0102 };
0103
0104 /**
0105  * struct stm32_timers_dma - STM32 timer DMA handling.
0106  * @completion:     end of DMA transfer completion
0107  * @phys_base:      control registers physical base address
0108  * @lock:       protect DMA access
0109  * @chan:       DMA channel in use
0110  * @chans:      DMA channels available for this timer instance
0111  */
0112 struct stm32_timers_dma {
0113     struct completion completion;
0114     phys_addr_t phys_base;
0115     struct mutex lock;
0116     struct dma_chan *chan;
0117     struct dma_chan *chans[STM32_TIMERS_MAX_DMAS];
0118 };
0119
0120 struct stm32_timers {
0121     struct clk *clk;
0122     struct regmap *regmap;
0123     u32 max_arr;
0124     struct stm32_timers_dma dma; /* Only to be used by the parent */
0125 };
0126
0127 #if IS_REACHABLE(CONFIG_MFD_STM32_TIMERS)
0128 int stm32_timers_dma_burst_read(struct device *dev, u32 *buf,
0129                 enum stm32_timers_dmas id, u32 reg,
0130                 unsigned int num_reg, unsigned int bursts,
0131                 unsigned long tmo_ms);
0132 #else
0133 static inline int stm32_timers_dma_burst_read(struct device *dev, u32 *buf,
0134                           enum stm32_timers_dmas id,
0135                           u32 reg,
0136                           unsigned int num_reg,
0137                           unsigned int bursts,
0138                           unsigned long tmo_ms)
0139 {
0140     return -ENODEV;
0141 }
0142 #endif
0143 #endif