linux/mfd/stm32-lptimer.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * STM32 Low-Power Timer parent driver.
0004  * Copyright (C) STMicroelectronics 2017
0005  * Author: Fabrice Gasnier <fabrice.gasnier@st.com>
0006  * Inspired by Benjamin Gaignard's stm32-timers driver
0007  */
0008
0009 #ifndef _LINUX_STM32_LPTIMER_H_
0010 #define _LINUX_STM32_LPTIMER_H_
0011
0012 #include <linux/clk.h>
0013 #include <linux/regmap.h>
0014
0015 #define STM32_LPTIM_ISR     0x00    /* Interrupt and Status Reg  */
0016 #define STM32_LPTIM_ICR     0x04    /* Interrupt Clear Reg       */
0017 #define STM32_LPTIM_IER     0x08    /* Interrupt Enable Reg      */
0018 #define STM32_LPTIM_CFGR    0x0C    /* Configuration Reg         */
0019 #define STM32_LPTIM_CR      0x10    /* Control Reg               */
0020 #define STM32_LPTIM_CMP     0x14    /* Compare Reg               */
0021 #define STM32_LPTIM_ARR     0x18    /* Autoreload Reg            */
0022 #define STM32_LPTIM_CNT     0x1C    /* Counter Reg               */
0023
0024 /* STM32_LPTIM_ISR - bit fields */
0025 #define STM32_LPTIM_CMPOK_ARROK     GENMASK(4, 3)
0026 #define STM32_LPTIM_ARROK       BIT(4)
0027 #define STM32_LPTIM_CMPOK       BIT(3)
0028
0029 /* STM32_LPTIM_ICR - bit fields */
0030 #define STM32_LPTIM_ARRMCF      BIT(1)
0031 #define STM32_LPTIM_CMPOKCF_ARROKCF GENMASK(4, 3)
0032
0033 /* STM32_LPTIM_IER - bit flieds */
0034 #define STM32_LPTIM_ARRMIE  BIT(1)
0035
0036 /* STM32_LPTIM_CR - bit fields */
0037 #define STM32_LPTIM_CNTSTRT BIT(2)
0038 #define STM32_LPTIM_SNGSTRT BIT(1)
0039 #define STM32_LPTIM_ENABLE  BIT(0)
0040
0041 /* STM32_LPTIM_CFGR - bit fields */
0042 #define STM32_LPTIM_ENC     BIT(24)
0043 #define STM32_LPTIM_COUNTMODE   BIT(23)
0044 #define STM32_LPTIM_WAVPOL  BIT(21)
0045 #define STM32_LPTIM_PRESC   GENMASK(11, 9)
0046 #define STM32_LPTIM_CKPOL   GENMASK(2, 1)
0047
0048 /* STM32_LPTIM_CKPOL */
0049 #define STM32_LPTIM_CKPOL_RISING_EDGE   0
0050 #define STM32_LPTIM_CKPOL_FALLING_EDGE  1
0051 #define STM32_LPTIM_CKPOL_BOTH_EDGES    2
0052
0053 /* STM32_LPTIM_ARR */
0054 #define STM32_LPTIM_MAX_ARR 0xFFFF
0055
0056 /**
0057  * struct stm32_lptimer - STM32 Low-Power Timer data assigned by parent device
0058  * @clk: clock reference for this instance
0059  * @regmap: register map reference for this instance
0060  * @has_encoder: indicates this Low-Power Timer supports encoder mode
0061  */
0062 struct stm32_lptimer {
0063     struct clk *clk;
0064     struct regmap *regmap;
0065     bool has_encoder;
0066 };
0067
0068 #endif