linux/mfd/si476x-platform.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * include/media/si476x-platform.h -- Platform data specific definitions
0004  *
0005  * Copyright (C) 2013 Andrey Smirnov
0006  *
0007  * Author: Andrey Smirnov <andrew.smirnov@gmail.com>
0008  */
0009
0010 #ifndef __SI476X_PLATFORM_H__
0011 #define __SI476X_PLATFORM_H__
0012
0013 /* It is possible to select one of the four adresses using pins A0
0014  * and A1 on SI476x */
0015 #define SI476X_I2C_ADDR_1   0x60
0016 #define SI476X_I2C_ADDR_2   0x61
0017 #define SI476X_I2C_ADDR_3   0x62
0018 #define SI476X_I2C_ADDR_4   0x63
0019
0020 enum si476x_iqclk_config {
0021     SI476X_IQCLK_NOOP = 0,
0022     SI476X_IQCLK_TRISTATE = 1,
0023     SI476X_IQCLK_IQ = 21,
0024 };
0025 enum si476x_iqfs_config {
0026     SI476X_IQFS_NOOP = 0,
0027     SI476X_IQFS_TRISTATE = 1,
0028     SI476X_IQFS_IQ = 21,
0029 };
0030 enum si476x_iout_config {
0031     SI476X_IOUT_NOOP = 0,
0032     SI476X_IOUT_TRISTATE = 1,
0033     SI476X_IOUT_OUTPUT = 22,
0034 };
0035 enum si476x_qout_config {
0036     SI476X_QOUT_NOOP = 0,
0037     SI476X_QOUT_TRISTATE = 1,
0038     SI476X_QOUT_OUTPUT = 22,
0039 };
0040
0041 enum si476x_dclk_config {
0042     SI476X_DCLK_NOOP      = 0,
0043     SI476X_DCLK_TRISTATE  = 1,
0044     SI476X_DCLK_DAUDIO    = 10,
0045 };
0046
0047 enum si476x_dfs_config {
0048     SI476X_DFS_NOOP      = 0,
0049     SI476X_DFS_TRISTATE  = 1,
0050     SI476X_DFS_DAUDIO    = 10,
0051 };
0052
0053 enum si476x_dout_config {
0054     SI476X_DOUT_NOOP       = 0,
0055     SI476X_DOUT_TRISTATE   = 1,
0056     SI476X_DOUT_I2S_OUTPUT = 12,
0057     SI476X_DOUT_I2S_INPUT  = 13,
0058 };
0059
0060 enum si476x_xout_config {
0061     SI476X_XOUT_NOOP        = 0,
0062     SI476X_XOUT_TRISTATE    = 1,
0063     SI476X_XOUT_I2S_INPUT   = 13,
0064     SI476X_XOUT_MODE_SELECT = 23,
0065 };
0066
0067 enum si476x_icin_config {
0068     SI476X_ICIN_NOOP    = 0,
0069     SI476X_ICIN_TRISTATE    = 1,
0070     SI476X_ICIN_GPO1_HIGH   = 2,
0071     SI476X_ICIN_GPO1_LOW    = 3,
0072     SI476X_ICIN_IC_LINK = 30,
0073 };
0074
0075 enum si476x_icip_config {
0076     SI476X_ICIP_NOOP    = 0,
0077     SI476X_ICIP_TRISTATE    = 1,
0078     SI476X_ICIP_GPO2_HIGH   = 2,
0079     SI476X_ICIP_GPO2_LOW    = 3,
0080     SI476X_ICIP_IC_LINK = 30,
0081 };
0082
0083 enum si476x_icon_config {
0084     SI476X_ICON_NOOP    = 0,
0085     SI476X_ICON_TRISTATE    = 1,
0086     SI476X_ICON_I2S     = 10,
0087     SI476X_ICON_IC_LINK = 30,
0088 };
0089
0090 enum si476x_icop_config {
0091     SI476X_ICOP_NOOP    = 0,
0092     SI476X_ICOP_TRISTATE    = 1,
0093     SI476X_ICOP_I2S     = 10,
0094     SI476X_ICOP_IC_LINK = 30,
0095 };
0096
0097
0098 enum si476x_lrout_config {
0099     SI476X_LROUT_NOOP   = 0,
0100     SI476X_LROUT_TRISTATE   = 1,
0101     SI476X_LROUT_AUDIO  = 2,
0102     SI476X_LROUT_MPX    = 3,
0103 };
0104
0105
0106 enum si476x_intb_config {
0107     SI476X_INTB_NOOP     = 0,
0108     SI476X_INTB_TRISTATE = 1,
0109     SI476X_INTB_DAUDIO   = 10,
0110     SI476X_INTB_IRQ      = 40,
0111 };
0112
0113 enum si476x_a1_config {
0114     SI476X_A1_NOOP     = 0,
0115     SI476X_A1_TRISTATE = 1,
0116     SI476X_A1_IRQ      = 40,
0117 };
0118
0119
0120 struct si476x_pinmux {
0121     enum si476x_dclk_config  dclk;
0122     enum si476x_dfs_config   dfs;
0123     enum si476x_dout_config  dout;
0124     enum si476x_xout_config  xout;
0125
0126     enum si476x_iqclk_config iqclk;
0127     enum si476x_iqfs_config  iqfs;
0128     enum si476x_iout_config  iout;
0129     enum si476x_qout_config  qout;
0130
0131     enum si476x_icin_config  icin;
0132     enum si476x_icip_config  icip;
0133     enum si476x_icon_config  icon;
0134     enum si476x_icop_config  icop;
0135
0136     enum si476x_lrout_config lrout;
0137
0138     enum si476x_intb_config  intb;
0139     enum si476x_a1_config    a1;
0140 };
0141
0142 enum si476x_ibias6x {
0143     SI476X_IBIAS6X_OTHER            = 0,
0144     SI476X_IBIAS6X_RCVR1_NON_4MHZ_CLK   = 1,
0145 };
0146
0147 enum si476x_xstart {
0148     SI476X_XSTART_MULTIPLE_TUNER    = 0x11,
0149     SI476X_XSTART_NORMAL        = 0x77,
0150 };
0151
0152 enum si476x_freq {
0153     SI476X_FREQ_4_MHZ       = 0,
0154     SI476X_FREQ_37P209375_MHZ   = 1,
0155     SI476X_FREQ_36P4_MHZ        = 2,
0156     SI476X_FREQ_37P8_MHZ        =  3,
0157 };
0158
0159 enum si476x_xmode {
0160     SI476X_XMODE_CRYSTAL_RCVR1  = 1,
0161     SI476X_XMODE_EXT_CLOCK      = 2,
0162     SI476X_XMODE_CRYSTAL_RCVR2_3    = 3,
0163 };
0164
0165 enum si476x_xbiashc {
0166     SI476X_XBIASHC_SINGLE_RECEIVER = 0,
0167     SI476X_XBIASHC_MULTIPLE_RECEIVER = 1,
0168 };
0169
0170 enum si476x_xbias {
0171     SI476X_XBIAS_RCVR2_3    = 0,
0172     SI476X_XBIAS_4MHZ_RCVR1 = 3,
0173     SI476X_XBIAS_RCVR1  = 7,
0174 };
0175
0176 enum si476x_func {
0177     SI476X_FUNC_BOOTLOADER  = 0,
0178     SI476X_FUNC_FM_RECEIVER = 1,
0179     SI476X_FUNC_AM_RECEIVER = 2,
0180     SI476X_FUNC_WB_RECEIVER = 3,
0181 };
0182
0183
0184 /**
0185  * @xcload: Selects the amount of additional on-chip capacitance to
0186  *          be connected between XTAL1 and gnd and between XTAL2 and
0187  *          GND. One half of the capacitance value shown here is the
0188  *          additional load capacitance presented to the xtal. The
0189  *          minimum step size is 0.277 pF. Recommended value is 0x28
0190  *          but it will be layout dependent. Range is 0–0x3F i.e.
0191  *          (0–16.33 pF)
0192  * @ctsien: enable CTSINT(interrupt request when CTS condition
0193  *          arises) when set
0194  * @intsel: when set A1 pin becomes the interrupt pin; otherwise,
0195  *          INTB is the interrupt pin
0196  * @func:   selects the boot function of the device. I.e.
0197  *          SI476X_BOOTLOADER  - Boot loader
0198  *          SI476X_FM_RECEIVER - FM receiver
0199  *          SI476X_AM_RECEIVER - AM receiver
0200  *          SI476X_WB_RECEIVER - Weatherband receiver
0201  * @freq:   oscillator's crystal frequency:
0202  *          SI476X_XTAL_37P209375_MHZ - 37.209375 Mhz
0203  *          SI476X_XTAL_36P4_MHZ      - 36.4 Mhz
0204  *          SI476X_XTAL_37P8_MHZ      - 37.8 Mhz
0205  */
0206 struct si476x_power_up_args {
0207     enum si476x_ibias6x ibias6x;
0208     enum si476x_xstart  xstart;
0209     u8   xcload;
0210     bool fastboot;
0211     enum si476x_xbiashc xbiashc;
0212     enum si476x_xbias   xbias;
0213     enum si476x_func    func;
0214     enum si476x_freq    freq;
0215     enum si476x_xmode   xmode;
0216 };
0217
0218
0219 /**
0220  * enum si476x_phase_diversity_mode - possbile phase diversity modes
0221  * for SI4764/5/6/7 chips.
0222  *
0223  * @SI476X_PHDIV_DISABLED:      Phase diversity feature is
0224  *                  disabled.
0225  * @SI476X_PHDIV_PRIMARY_COMBINING: Tuner works as a primary tuner
0226  *                  in combination with a
0227  *                  secondary one.
0228  * @SI476X_PHDIV_PRIMARY_ANTENNA:   Tuner works as a primary tuner
0229  *                  using only its own antenna.
0230  * @SI476X_PHDIV_SECONDARY_ANTENNA: Tuner works as a primary tuner
0231  *                  usning seconary tuner's antenna.
0232  * @SI476X_PHDIV_SECONDARY_COMBINING:   Tuner works as a secondary
0233  *                  tuner in combination with the
0234  *                  primary one.
0235  */
0236 enum si476x_phase_diversity_mode {
0237     SI476X_PHDIV_DISABLED           = 0,
0238     SI476X_PHDIV_PRIMARY_COMBINING      = 1,
0239     SI476X_PHDIV_PRIMARY_ANTENNA        = 2,
0240     SI476X_PHDIV_SECONDARY_ANTENNA      = 3,
0241     SI476X_PHDIV_SECONDARY_COMBINING    = 5,
0242 };
0243
0244
0245 /*
0246  * Platform dependent definition
0247  */
0248 struct si476x_platform_data {
0249     int gpio_reset; /* < 0 if not used */
0250
0251     struct si476x_power_up_args power_up_parameters;
0252     enum si476x_phase_diversity_mode diversity_mode;
0253
0254     struct si476x_pinmux pinmux;
0255 };
0256
0257
0258 #endif /* __SI476X_PLATFORM_H__ */