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0007 #ifndef __LINUX_MFD_S2MPS15_H
0008 #define __LINUX_MFD_S2MPS15_H
0009
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0011 enum s2mps15_reg {
0012 S2MPS15_REG_ID,
0013 S2MPS15_REG_INT1,
0014 S2MPS15_REG_INT2,
0015 S2MPS15_REG_INT3,
0016 S2MPS15_REG_INT1M,
0017 S2MPS15_REG_INT2M,
0018 S2MPS15_REG_INT3M,
0019 S2MPS15_REG_ST1,
0020 S2MPS15_REG_ST2,
0021 S2MPS15_REG_PWRONSRC,
0022 S2MPS15_REG_OFFSRC,
0023 S2MPS15_REG_BU_CHG,
0024 S2MPS15_REG_RTC_BUF,
0025 S2MPS15_REG_CTRL1,
0026 S2MPS15_REG_CTRL2,
0027 S2MPS15_REG_RSVD1,
0028 S2MPS15_REG_RSVD2,
0029 S2MPS15_REG_RSVD3,
0030 S2MPS15_REG_RSVD4,
0031 S2MPS15_REG_RSVD5,
0032 S2MPS15_REG_RSVD6,
0033 S2MPS15_REG_CTRL3,
0034 S2MPS15_REG_RSVD7,
0035 S2MPS15_REG_RSVD8,
0036 S2MPS15_REG_RSVD9,
0037 S2MPS15_REG_B1CTRL1,
0038 S2MPS15_REG_B1CTRL2,
0039 S2MPS15_REG_B2CTRL1,
0040 S2MPS15_REG_B2CTRL2,
0041 S2MPS15_REG_B3CTRL1,
0042 S2MPS15_REG_B3CTRL2,
0043 S2MPS15_REG_B4CTRL1,
0044 S2MPS15_REG_B4CTRL2,
0045 S2MPS15_REG_B5CTRL1,
0046 S2MPS15_REG_B5CTRL2,
0047 S2MPS15_REG_B6CTRL1,
0048 S2MPS15_REG_B6CTRL2,
0049 S2MPS15_REG_B7CTRL1,
0050 S2MPS15_REG_B7CTRL2,
0051 S2MPS15_REG_B8CTRL1,
0052 S2MPS15_REG_B8CTRL2,
0053 S2MPS15_REG_B9CTRL1,
0054 S2MPS15_REG_B9CTRL2,
0055 S2MPS15_REG_B10CTRL1,
0056 S2MPS15_REG_B10CTRL2,
0057 S2MPS15_REG_BBCTRL1,
0058 S2MPS15_REG_BBCTRL2,
0059 S2MPS15_REG_BRAMP,
0060 S2MPS15_REG_LDODVS1,
0061 S2MPS15_REG_LDODVS2,
0062 S2MPS15_REG_LDODVS3,
0063 S2MPS15_REG_LDODVS4,
0064 S2MPS15_REG_L1CTRL,
0065 S2MPS15_REG_L2CTRL,
0066 S2MPS15_REG_L3CTRL,
0067 S2MPS15_REG_L4CTRL,
0068 S2MPS15_REG_L5CTRL,
0069 S2MPS15_REG_L6CTRL,
0070 S2MPS15_REG_L7CTRL,
0071 S2MPS15_REG_L8CTRL,
0072 S2MPS15_REG_L9CTRL,
0073 S2MPS15_REG_L10CTRL,
0074 S2MPS15_REG_L11CTRL,
0075 S2MPS15_REG_L12CTRL,
0076 S2MPS15_REG_L13CTRL,
0077 S2MPS15_REG_L14CTRL,
0078 S2MPS15_REG_L15CTRL,
0079 S2MPS15_REG_L16CTRL,
0080 S2MPS15_REG_L17CTRL,
0081 S2MPS15_REG_L18CTRL,
0082 S2MPS15_REG_L19CTRL,
0083 S2MPS15_REG_L20CTRL,
0084 S2MPS15_REG_L21CTRL,
0085 S2MPS15_REG_L22CTRL,
0086 S2MPS15_REG_L23CTRL,
0087 S2MPS15_REG_L24CTRL,
0088 S2MPS15_REG_L25CTRL,
0089 S2MPS15_REG_L26CTRL,
0090 S2MPS15_REG_L27CTRL,
0091 S2MPS15_REG_LDODSCH1,
0092 S2MPS15_REG_LDODSCH2,
0093 S2MPS15_REG_LDODSCH3,
0094 S2MPS15_REG_LDODSCH4,
0095 };
0096
0097
0098 enum s2mps15_regulators {
0099 S2MPS15_LDO1,
0100 S2MPS15_LDO2,
0101 S2MPS15_LDO3,
0102 S2MPS15_LDO4,
0103 S2MPS15_LDO5,
0104 S2MPS15_LDO6,
0105 S2MPS15_LDO7,
0106 S2MPS15_LDO8,
0107 S2MPS15_LDO9,
0108 S2MPS15_LDO10,
0109 S2MPS15_LDO11,
0110 S2MPS15_LDO12,
0111 S2MPS15_LDO13,
0112 S2MPS15_LDO14,
0113 S2MPS15_LDO15,
0114 S2MPS15_LDO16,
0115 S2MPS15_LDO17,
0116 S2MPS15_LDO18,
0117 S2MPS15_LDO19,
0118 S2MPS15_LDO20,
0119 S2MPS15_LDO21,
0120 S2MPS15_LDO22,
0121 S2MPS15_LDO23,
0122 S2MPS15_LDO24,
0123 S2MPS15_LDO25,
0124 S2MPS15_LDO26,
0125 S2MPS15_LDO27,
0126 S2MPS15_BUCK1,
0127 S2MPS15_BUCK2,
0128 S2MPS15_BUCK3,
0129 S2MPS15_BUCK4,
0130 S2MPS15_BUCK5,
0131 S2MPS15_BUCK6,
0132 S2MPS15_BUCK7,
0133 S2MPS15_BUCK8,
0134 S2MPS15_BUCK9,
0135 S2MPS15_BUCK10,
0136 S2MPS15_BUCK11,
0137 S2MPS15_REGULATOR_MAX,
0138 };
0139
0140 #define S2MPS15_LDO_VSEL_MASK (0x3F)
0141 #define S2MPS15_BUCK_VSEL_MASK (0xFF)
0142
0143 #define S2MPS15_ENABLE_SHIFT (0x06)
0144 #define S2MPS15_ENABLE_MASK (0x03 << S2MPS15_ENABLE_SHIFT)
0145
0146 #define S2MPS15_LDO_N_VOLTAGES (S2MPS15_LDO_VSEL_MASK + 1)
0147 #define S2MPS15_BUCK_N_VOLTAGES (S2MPS15_BUCK_VSEL_MASK + 1)
0148
0149 #endif