mfd/samsung/irq.h

0001 /* SPDX-License-Identifier: GPL-2.0+ */
0002 /*
0003  * Copyright (c) 2012 Samsung Electronics Co., Ltd
0004  *              http://www.samsung.com
0005  */
0006
0007 #ifndef __LINUX_MFD_SEC_IRQ_H
0008 #define __LINUX_MFD_SEC_IRQ_H
0009
0010 enum s2mpa01_irq {
0011     S2MPA01_IRQ_PWRONF,
0012     S2MPA01_IRQ_PWRONR,
0013     S2MPA01_IRQ_JIGONBF,
0014     S2MPA01_IRQ_JIGONBR,
0015     S2MPA01_IRQ_ACOKBF,
0016     S2MPA01_IRQ_ACOKBR,
0017     S2MPA01_IRQ_PWRON1S,
0018     S2MPA01_IRQ_MRB,
0019
0020     S2MPA01_IRQ_RTC60S,
0021     S2MPA01_IRQ_RTCA1,
0022     S2MPA01_IRQ_RTCA0,
0023     S2MPA01_IRQ_SMPL,
0024     S2MPA01_IRQ_RTC1S,
0025     S2MPA01_IRQ_WTSR,
0026
0027     S2MPA01_IRQ_INT120C,
0028     S2MPA01_IRQ_INT140C,
0029     S2MPA01_IRQ_LDO3_TSD,
0030     S2MPA01_IRQ_B16_TSD,
0031     S2MPA01_IRQ_B24_TSD,
0032     S2MPA01_IRQ_B35_TSD,
0033
0034     S2MPA01_IRQ_NR,
0035 };
0036
0037 #define S2MPA01_IRQ_PWRONF_MASK     (1 << 0)
0038 #define S2MPA01_IRQ_PWRONR_MASK     (1 << 1)
0039 #define S2MPA01_IRQ_JIGONBF_MASK    (1 << 2)
0040 #define S2MPA01_IRQ_JIGONBR_MASK    (1 << 3)
0041 #define S2MPA01_IRQ_ACOKBF_MASK     (1 << 4)
0042 #define S2MPA01_IRQ_ACOKBR_MASK     (1 << 5)
0043 #define S2MPA01_IRQ_PWRON1S_MASK    (1 << 6)
0044 #define S2MPA01_IRQ_MRB_MASK        (1 << 7)
0045
0046 #define S2MPA01_IRQ_RTC60S_MASK     (1 << 0)
0047 #define S2MPA01_IRQ_RTCA1_MASK      (1 << 1)
0048 #define S2MPA01_IRQ_RTCA0_MASK      (1 << 2)
0049 #define S2MPA01_IRQ_SMPL_MASK       (1 << 3)
0050 #define S2MPA01_IRQ_RTC1S_MASK      (1 << 4)
0051 #define S2MPA01_IRQ_WTSR_MASK       (1 << 5)
0052
0053 #define S2MPA01_IRQ_INT120C_MASK    (1 << 0)
0054 #define S2MPA01_IRQ_INT140C_MASK    (1 << 1)
0055 #define S2MPA01_IRQ_LDO3_TSD_MASK   (1 << 2)
0056 #define S2MPA01_IRQ_B16_TSD_MASK    (1 << 3)
0057 #define S2MPA01_IRQ_B24_TSD_MASK    (1 << 4)
0058 #define S2MPA01_IRQ_B35_TSD_MASK    (1 << 5)
0059
0060 enum s2mps11_irq {
0061     S2MPS11_IRQ_PWRONF,
0062     S2MPS11_IRQ_PWRONR,
0063     S2MPS11_IRQ_JIGONBF,
0064     S2MPS11_IRQ_JIGONBR,
0065     S2MPS11_IRQ_ACOKBF,
0066     S2MPS11_IRQ_ACOKBR,
0067     S2MPS11_IRQ_PWRON1S,
0068     S2MPS11_IRQ_MRB,
0069
0070     S2MPS11_IRQ_RTC60S,
0071     S2MPS11_IRQ_RTCA1,
0072     S2MPS11_IRQ_RTCA0,
0073     S2MPS11_IRQ_SMPL,
0074     S2MPS11_IRQ_RTC1S,
0075     S2MPS11_IRQ_WTSR,
0076
0077     S2MPS11_IRQ_INT120C,
0078     S2MPS11_IRQ_INT140C,
0079
0080     S2MPS11_IRQ_NR,
0081 };
0082
0083 #define S2MPS11_IRQ_PWRONF_MASK     (1 << 0)
0084 #define S2MPS11_IRQ_PWRONR_MASK     (1 << 1)
0085 #define S2MPS11_IRQ_JIGONBF_MASK    (1 << 2)
0086 #define S2MPS11_IRQ_JIGONBR_MASK    (1 << 3)
0087 #define S2MPS11_IRQ_ACOKBF_MASK     (1 << 4)
0088 #define S2MPS11_IRQ_ACOKBR_MASK     (1 << 5)
0089 #define S2MPS11_IRQ_PWRON1S_MASK    (1 << 6)
0090 #define S2MPS11_IRQ_MRB_MASK        (1 << 7)
0091
0092 #define S2MPS11_IRQ_RTC60S_MASK     (1 << 0)
0093 #define S2MPS11_IRQ_RTCA1_MASK      (1 << 1)
0094 #define S2MPS11_IRQ_RTCA0_MASK      (1 << 2)
0095 #define S2MPS11_IRQ_SMPL_MASK       (1 << 3)
0096 #define S2MPS11_IRQ_RTC1S_MASK      (1 << 4)
0097 #define S2MPS11_IRQ_WTSR_MASK       (1 << 5)
0098
0099 #define S2MPS11_IRQ_INT120C_MASK    (1 << 0)
0100 #define S2MPS11_IRQ_INT140C_MASK    (1 << 1)
0101
0102 enum s2mps14_irq {
0103     S2MPS14_IRQ_PWRONF,
0104     S2MPS14_IRQ_PWRONR,
0105     S2MPS14_IRQ_JIGONBF,
0106     S2MPS14_IRQ_JIGONBR,
0107     S2MPS14_IRQ_ACOKBF,
0108     S2MPS14_IRQ_ACOKBR,
0109     S2MPS14_IRQ_PWRON1S,
0110     S2MPS14_IRQ_MRB,
0111
0112     S2MPS14_IRQ_RTC60S,
0113     S2MPS14_IRQ_RTCA1,
0114     S2MPS14_IRQ_RTCA0,
0115     S2MPS14_IRQ_SMPL,
0116     S2MPS14_IRQ_RTC1S,
0117     S2MPS14_IRQ_WTSR,
0118
0119     S2MPS14_IRQ_INT120C,
0120     S2MPS14_IRQ_INT140C,
0121     S2MPS14_IRQ_TSD,
0122
0123     S2MPS14_IRQ_NR,
0124 };
0125
0126 enum s2mpu02_irq {
0127     S2MPU02_IRQ_PWRONF,
0128     S2MPU02_IRQ_PWRONR,
0129     S2MPU02_IRQ_JIGONBF,
0130     S2MPU02_IRQ_JIGONBR,
0131     S2MPU02_IRQ_ACOKBF,
0132     S2MPU02_IRQ_ACOKBR,
0133     S2MPU02_IRQ_PWRON1S,
0134     S2MPU02_IRQ_MRB,
0135
0136     S2MPU02_IRQ_RTC60S,
0137     S2MPU02_IRQ_RTCA1,
0138     S2MPU02_IRQ_RTCA0,
0139     S2MPU02_IRQ_SMPL,
0140     S2MPU02_IRQ_RTC1S,
0141     S2MPU02_IRQ_WTSR,
0142
0143     S2MPU02_IRQ_INT120C,
0144     S2MPU02_IRQ_INT140C,
0145     S2MPU02_IRQ_TSD,
0146
0147     S2MPU02_IRQ_NR,
0148 };
0149
0150 /* Masks for interrupts are the same as in s2mps11 */
0151 #define S2MPS14_IRQ_TSD_MASK        (1 << 2)
0152
0153 enum s5m8767_irq {
0154     S5M8767_IRQ_PWRR,
0155     S5M8767_IRQ_PWRF,
0156     S5M8767_IRQ_PWR1S,
0157     S5M8767_IRQ_JIGR,
0158     S5M8767_IRQ_JIGF,
0159     S5M8767_IRQ_LOWBAT2,
0160     S5M8767_IRQ_LOWBAT1,
0161
0162     S5M8767_IRQ_MRB,
0163     S5M8767_IRQ_DVSOK2,
0164     S5M8767_IRQ_DVSOK3,
0165     S5M8767_IRQ_DVSOK4,
0166
0167     S5M8767_IRQ_RTC60S,
0168     S5M8767_IRQ_RTCA1,
0169     S5M8767_IRQ_RTCA2,
0170     S5M8767_IRQ_SMPL,
0171     S5M8767_IRQ_RTC1S,
0172     S5M8767_IRQ_WTSR,
0173
0174     S5M8767_IRQ_NR,
0175 };
0176
0177 #define S5M8767_IRQ_PWRR_MASK       (1 << 0)
0178 #define S5M8767_IRQ_PWRF_MASK       (1 << 1)
0179 #define S5M8767_IRQ_PWR1S_MASK      (1 << 3)
0180 #define S5M8767_IRQ_JIGR_MASK       (1 << 4)
0181 #define S5M8767_IRQ_JIGF_MASK       (1 << 5)
0182 #define S5M8767_IRQ_LOWBAT2_MASK    (1 << 6)
0183 #define S5M8767_IRQ_LOWBAT1_MASK    (1 << 7)
0184
0185 #define S5M8767_IRQ_MRB_MASK        (1 << 2)
0186 #define S5M8767_IRQ_DVSOK2_MASK     (1 << 3)
0187 #define S5M8767_IRQ_DVSOK3_MASK     (1 << 4)
0188 #define S5M8767_IRQ_DVSOK4_MASK     (1 << 5)
0189
0190 #define S5M8767_IRQ_RTC60S_MASK     (1 << 0)
0191 #define S5M8767_IRQ_RTCA1_MASK      (1 << 1)
0192 #define S5M8767_IRQ_RTCA2_MASK      (1 << 2)
0193 #define S5M8767_IRQ_SMPL_MASK       (1 << 3)
0194 #define S5M8767_IRQ_RTC1S_MASK      (1 << 4)
0195 #define S5M8767_IRQ_WTSR_MASK       (1 << 5)
0196
0197 enum s5m8763_irq {
0198     S5M8763_IRQ_DCINF,
0199     S5M8763_IRQ_DCINR,
0200     S5M8763_IRQ_JIGF,
0201     S5M8763_IRQ_JIGR,
0202     S5M8763_IRQ_PWRONF,
0203     S5M8763_IRQ_PWRONR,
0204
0205     S5M8763_IRQ_WTSREVNT,
0206     S5M8763_IRQ_SMPLEVNT,
0207     S5M8763_IRQ_ALARM1,
0208     S5M8763_IRQ_ALARM0,
0209
0210     S5M8763_IRQ_ONKEY1S,
0211     S5M8763_IRQ_TOPOFFR,
0212     S5M8763_IRQ_DCINOVPR,
0213     S5M8763_IRQ_CHGRSTF,
0214     S5M8763_IRQ_DONER,
0215     S5M8763_IRQ_CHGFAULT,
0216
0217     S5M8763_IRQ_LOBAT1,
0218     S5M8763_IRQ_LOBAT2,
0219
0220     S5M8763_IRQ_NR,
0221 };
0222
0223 #define S5M8763_IRQ_DCINF_MASK      (1 << 2)
0224 #define S5M8763_IRQ_DCINR_MASK      (1 << 3)
0225 #define S5M8763_IRQ_JIGF_MASK       (1 << 4)
0226 #define S5M8763_IRQ_JIGR_MASK       (1 << 5)
0227 #define S5M8763_IRQ_PWRONF_MASK     (1 << 6)
0228 #define S5M8763_IRQ_PWRONR_MASK     (1 << 7)
0229
0230 #define S5M8763_IRQ_WTSREVNT_MASK   (1 << 0)
0231 #define S5M8763_IRQ_SMPLEVNT_MASK   (1 << 1)
0232 #define S5M8763_IRQ_ALARM1_MASK     (1 << 2)
0233 #define S5M8763_IRQ_ALARM0_MASK     (1 << 3)
0234
0235 #define S5M8763_IRQ_ONKEY1S_MASK    (1 << 0)
0236 #define S5M8763_IRQ_TOPOFFR_MASK    (1 << 2)
0237 #define S5M8763_IRQ_DCINOVPR_MASK   (1 << 3)
0238 #define S5M8763_IRQ_CHGRSTF_MASK    (1 << 4)
0239 #define S5M8763_IRQ_DONER_MASK      (1 << 5)
0240 #define S5M8763_IRQ_CHGFAULT_MASK   (1 << 7)
0241
0242 #define S5M8763_IRQ_LOBAT1_MASK     (1 << 0)
0243 #define S5M8763_IRQ_LOBAT2_MASK     (1 << 1)
0244
0245 #define S5M8763_ENRAMP                  (1 << 4)
0246
0247 #endif /*  __LINUX_MFD_SEC_IRQ_H */