linux/mfd/rt5033-private.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * MFD core driver for Richtek RT5033
0004  *
0005  * Copyright (C) 2014 Samsung Electronics, Co., Ltd.
0006  * Author: Beomho Seo <beomho.seo@samsung.com>
0007  */
0008
0009 #ifndef __RT5033_PRIVATE_H__
0010 #define __RT5033_PRIVATE_H__
0011
0012 enum rt5033_reg {
0013     RT5033_REG_CHG_STAT     = 0x00,
0014     RT5033_REG_CHG_CTRL1        = 0x01,
0015     RT5033_REG_CHG_CTRL2        = 0x02,
0016     RT5033_REG_DEVICE_ID        = 0x03,
0017     RT5033_REG_CHG_CTRL3        = 0x04,
0018     RT5033_REG_CHG_CTRL4        = 0x05,
0019     RT5033_REG_CHG_CTRL5        = 0x06,
0020     RT5033_REG_RT_CTRL0     = 0x07,
0021     RT5033_REG_CHG_RESET        = 0x08,
0022     /* Reserved 0x09~0x18 */
0023     RT5033_REG_RT_CTRL1     = 0x19,
0024     /* Reserved 0x1A~0x20 */
0025     RT5033_REG_FLED_FUNCTION1   = 0x21,
0026     RT5033_REG_FLED_FUNCTION2   = 0x22,
0027     RT5033_REG_FLED_STROBE_CTRL1    = 0x23,
0028     RT5033_REG_FLED_STROBE_CTRL2    = 0x24,
0029     RT5033_REG_FLED_CTRL1       = 0x25,
0030     RT5033_REG_FLED_CTRL2       = 0x26,
0031     RT5033_REG_FLED_CTRL3       = 0x27,
0032     RT5033_REG_FLED_CTRL4       = 0x28,
0033     RT5033_REG_FLED_CTRL5       = 0x29,
0034     /* Reserved 0x2A~0x40 */
0035     RT5033_REG_CTRL         = 0x41,
0036     RT5033_REG_BUCK_CTRL        = 0x42,
0037     RT5033_REG_LDO_CTRL     = 0x43,
0038     /* Reserved 0x44~0x46 */
0039     RT5033_REG_MANUAL_RESET_CTRL    = 0x47,
0040     /* Reserved 0x48~0x5F */
0041     RT5033_REG_CHG_IRQ1     = 0x60,
0042     RT5033_REG_CHG_IRQ2     = 0x61,
0043     RT5033_REG_CHG_IRQ3     = 0x62,
0044     RT5033_REG_CHG_IRQ1_CTRL    = 0x63,
0045     RT5033_REG_CHG_IRQ2_CTRL    = 0x64,
0046     RT5033_REG_CHG_IRQ3_CTRL    = 0x65,
0047     RT5033_REG_LED_IRQ_STAT     = 0x66,
0048     RT5033_REG_LED_IRQ_CTRL     = 0x67,
0049     RT5033_REG_PMIC_IRQ_STAT    = 0x68,
0050     RT5033_REG_PMIC_IRQ_CTRL    = 0x69,
0051     RT5033_REG_SHDN_CTRL        = 0x6A,
0052     RT5033_REG_OFF_EVENT        = 0x6B,
0053
0054     RT5033_REG_END,
0055 };
0056
0057 /* RT5033 Charger state register */
0058 #define RT5033_CHG_STAT_MASK        0x20
0059 #define RT5033_CHG_STAT_DISCHARGING 0x00
0060 #define RT5033_CHG_STAT_FULL        0x10
0061 #define RT5033_CHG_STAT_CHARGING    0x20
0062 #define RT5033_CHG_STAT_NOT_CHARGING    0x30
0063 #define RT5033_CHG_STAT_TYPE_MASK   0x60
0064 #define RT5033_CHG_STAT_TYPE_PRE    0x20
0065 #define RT5033_CHG_STAT_TYPE_FAST   0x60
0066
0067 /* RT5033 CHGCTRL1 register */
0068 #define RT5033_CHGCTRL1_IAICR_MASK  0xe0
0069 #define RT5033_CHGCTRL1_MODE_MASK   0x01
0070
0071 /* RT5033 CHGCTRL2 register */
0072 #define RT5033_CHGCTRL2_CV_MASK     0xfc
0073
0074 /* RT5033 CHGCTRL3 register */
0075 #define RT5033_CHGCTRL3_CFO_EN_MASK 0x40
0076 #define RT5033_CHGCTRL3_TIMER_MASK  0x38
0077 #define RT5033_CHGCTRL3_TIMER_EN_MASK   0x01
0078
0079 /* RT5033 CHGCTRL4 register */
0080 #define RT5033_CHGCTRL4_EOC_MASK    0x07
0081 #define RT5033_CHGCTRL4_IPREC_MASK  0x18
0082
0083 /* RT5033 CHGCTRL5 register */
0084 #define RT5033_CHGCTRL5_VPREC_MASK  0x0f
0085 #define RT5033_CHGCTRL5_ICHG_MASK   0xf0
0086 #define RT5033_CHGCTRL5_ICHG_SHIFT  0x04
0087 #define RT5033_CHG_MAX_CURRENT      0x0d
0088
0089 /* RT5033 RT CTRL1 register */
0090 #define RT5033_RT_CTRL1_UUG_MASK    0x02
0091 #define RT5033_RT_HZ_MASK       0x01
0092
0093 /* RT5033 control register */
0094 #define RT5033_CTRL_FCCM_BUCK_MASK      BIT(0)
0095 #define RT5033_CTRL_BUCKOMS_MASK        BIT(1)
0096 #define RT5033_CTRL_LDOOMS_MASK         BIT(2)
0097 #define RT5033_CTRL_SLDOOMS_MASK        BIT(3)
0098 #define RT5033_CTRL_EN_BUCK_MASK        BIT(4)
0099 #define RT5033_CTRL_EN_LDO_MASK         BIT(5)
0100 #define RT5033_CTRL_EN_SAFE_LDO_MASK        BIT(6)
0101 #define RT5033_CTRL_LDO_SLEEP_MASK      BIT(7)
0102
0103 /* RT5033 BUCK control register */
0104 #define RT5033_BUCK_CTRL_MASK           0x1f
0105
0106 /* RT5033 LDO control register */
0107 #define RT5033_LDO_CTRL_MASK            0x1f
0108
0109 /* RT5033 charger property - model, manufacturer */
0110
0111 #define RT5033_CHARGER_MODEL    "RT5033WSC Charger"
0112 #define RT5033_MANUFACTURER "Richtek Technology Corporation"
0113
0114 /*
0115  * RT5033 charger fast-charge current lmits (as in CHGCTRL1 register),
0116  * AICR mode limits the input current for example,
0117  * the AIRC 100 mode limits the input current to 100 mA.
0118  */
0119 #define RT5033_AICR_100_MODE            0x20
0120 #define RT5033_AICR_500_MODE            0x40
0121 #define RT5033_AICR_700_MODE            0x60
0122 #define RT5033_AICR_900_MODE            0x80
0123 #define RT5033_AICR_1500_MODE           0xc0
0124 #define RT5033_AICR_2000_MODE           0xe0
0125 #define RT5033_AICR_MODE_MASK           0xe0
0126
0127 /* RT5033 use internal timer need to set time */
0128 #define RT5033_FAST_CHARGE_TIMER4       0x00
0129 #define RT5033_FAST_CHARGE_TIMER6       0x01
0130 #define RT5033_FAST_CHARGE_TIMER8       0x02
0131 #define RT5033_FAST_CHARGE_TIMER9       0x03
0132 #define RT5033_FAST_CHARGE_TIMER12      0x04
0133 #define RT5033_FAST_CHARGE_TIMER14      0x05
0134 #define RT5033_FAST_CHARGE_TIMER16      0x06
0135
0136 #define RT5033_INT_TIMER_ENABLE         0x01
0137
0138 /* RT5033 charger termination enable mask */
0139 #define RT5033_TE_ENABLE_MASK           0x08
0140
0141 /*
0142  * RT5033 charger opa mode. RT50300 have two opa mode charger mode
0143  * and boost mode for OTG
0144  */
0145
0146 #define RT5033_CHARGER_MODE         0x00
0147 #define RT5033_BOOST_MODE           0x01
0148
0149 /* RT5033 charger termination enable */
0150 #define RT5033_TE_ENABLE            0x08
0151
0152 /* RT5033 charger CFO enable */
0153 #define RT5033_CFO_ENABLE           0x40
0154
0155 /* RT5033 charger constant charge voltage (as in CHGCTRL2 register), uV */
0156 #define RT5033_CHARGER_CONST_VOLTAGE_LIMIT_MIN  3650000U
0157 #define RT5033_CHARGER_CONST_VOLTAGE_STEP_NUM   25000U
0158 #define RT5033_CHARGER_CONST_VOLTAGE_LIMIT_MAX  4400000U
0159
0160 /* RT5033 charger pre-charge current limits (as in CHGCTRL4 register), uA */
0161 #define RT5033_CHARGER_PRE_CURRENT_LIMIT_MIN    350000U
0162 #define RT5033_CHARGER_PRE_CURRENT_STEP_NUM 100000U
0163 #define RT5033_CHARGER_PRE_CURRENT_LIMIT_MAX    650000U
0164
0165 /* RT5033 charger fast-charge current (as in CHGCTRL5 register), uA */
0166 #define RT5033_CHARGER_FAST_CURRENT_MIN     700000U
0167 #define RT5033_CHARGER_FAST_CURRENT_STEP_NUM    100000U
0168 #define RT5033_CHARGER_FAST_CURRENT_MAX     2000000U
0169
0170 /*
0171  * RT5033 charger const-charge end of charger current (
0172  * as in CHGCTRL4 register), uA
0173  */
0174 #define RT5033_CHARGER_EOC_MIN          150000U
0175 #define RT5033_CHARGER_EOC_REF          300000U
0176 #define RT5033_CHARGER_EOC_STEP_NUM1        50000U
0177 #define RT5033_CHARGER_EOC_STEP_NUM2        100000U
0178 #define RT5033_CHARGER_EOC_MAX          600000U
0179
0180 /*
0181  * RT5033 charger pre-charge threshold volt limits
0182  * (as in CHGCTRL5 register), uV
0183  */
0184
0185 #define RT5033_CHARGER_PRE_THRESHOLD_LIMIT_MIN  2300000U
0186 #define RT5033_CHARGER_PRE_THRESHOLD_STEP_NUM   100000U
0187 #define RT5033_CHARGER_PRE_THRESHOLD_LIMIT_MAX  3800000U
0188
0189 /*
0190  * RT5033 charger enable UUG, If UUG enable MOS auto control by H/W charger
0191  * circuit.
0192  */
0193 #define RT5033_CHARGER_UUG_ENABLE       0x02
0194
0195 /* RT5033 charger High impedance mode */
0196 #define RT5033_CHARGER_HZ_DISABLE       0x00
0197 #define RT5033_CHARGER_HZ_ENABLE        0x01
0198
0199 /* RT5033 regulator BUCK output voltage uV */
0200 #define RT5033_REGULATOR_BUCK_VOLTAGE_MIN       1000000U
0201 #define RT5033_REGULATOR_BUCK_VOLTAGE_MAX       3000000U
0202 #define RT5033_REGULATOR_BUCK_VOLTAGE_STEP      100000U
0203 #define RT5033_REGULATOR_BUCK_VOLTAGE_STEP_NUM      32
0204
0205 /* RT5033 regulator LDO output voltage uV */
0206 #define RT5033_REGULATOR_LDO_VOLTAGE_MIN        1200000U
0207 #define RT5033_REGULATOR_LDO_VOLTAGE_MAX        3000000U
0208 #define RT5033_REGULATOR_LDO_VOLTAGE_STEP       100000U
0209 #define RT5033_REGULATOR_LDO_VOLTAGE_STEP_NUM       32
0210
0211 /* RT5033 regulator SAFE LDO output voltage uV */
0212 #define RT5033_REGULATOR_SAFE_LDO_VOLTAGE       4900000U
0213
0214 enum rt5033_fuel_reg {
0215     RT5033_FUEL_REG_OCV_H       = 0x00,
0216     RT5033_FUEL_REG_OCV_L       = 0x01,
0217     RT5033_FUEL_REG_VBAT_H      = 0x02,
0218     RT5033_FUEL_REG_VBAT_L      = 0x03,
0219     RT5033_FUEL_REG_SOC_H       = 0x04,
0220     RT5033_FUEL_REG_SOC_L       = 0x05,
0221     RT5033_FUEL_REG_CTRL_H      = 0x06,
0222     RT5033_FUEL_REG_CTRL_L      = 0x07,
0223     RT5033_FUEL_REG_CRATE       = 0x08,
0224     RT5033_FUEL_REG_DEVICE_ID   = 0x09,
0225     RT5033_FUEL_REG_AVG_VOLT_H  = 0x0A,
0226     RT5033_FUEL_REG_AVG_VOLT_L  = 0x0B,
0227     RT5033_FUEL_REG_CONFIG_H    = 0x0C,
0228     RT5033_FUEL_REG_CONFIG_L    = 0x0D,
0229     /* Reserved 0x0E~0x0F */
0230     RT5033_FUEL_REG_IRQ_CTRL    = 0x10,
0231     RT5033_FUEL_REG_IRQ_FLAG    = 0x11,
0232     RT5033_FUEL_VMIN        = 0x12,
0233     RT5033_FUEL_SMIN        = 0x13,
0234     /* Reserved 0x14~0x1F */
0235     RT5033_FUEL_VGCOMP1     = 0x20,
0236     RT5033_FUEL_VGCOMP2     = 0x21,
0237     RT5033_FUEL_VGCOMP3     = 0x22,
0238     RT5033_FUEL_VGCOMP4     = 0x23,
0239     /* Reserved 0x24~0xFD */
0240     RT5033_FUEL_MFA_H       = 0xFE,
0241     RT5033_FUEL_MFA_L       = 0xFF,
0242
0243     RT5033_FUEL_REG_END,
0244 };
0245
0246 /* RT5033 fuel gauge battery present property */
0247 #define RT5033_FUEL_BAT_PRESENT     0x02
0248
0249 /* RT5033 PMIC interrupts */
0250 #define RT5033_PMIC_IRQ_BUCKOCP     BIT(2)
0251 #define RT5033_PMIC_IRQ_BUCKLV      BIT(3)
0252 #define RT5033_PMIC_IRQ_SAFELDOLV   BIT(4)
0253 #define RT5033_PMIC_IRQ_LDOLV       BIT(5)
0254 #define RT5033_PMIC_IRQ_OT      BIT(6)
0255 #define RT5033_PMIC_IRQ_VDDA_UV     BIT(7)
0256
0257 #endif /* __RT5033_PRIVATE_H__ */