linux/mfd/rohm-bd957x.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /* Copyright (C) 2021 ROHM Semiconductors */
0003
0004 #ifndef __LINUX_MFD_BD957X_H__
0005 #define __LINUX_MFD_BD957X_H__
0006
0007 enum {
0008     BD957X_VD50,
0009     BD957X_VD18,
0010     BD957X_VDDDR,
0011     BD957X_VD10,
0012     BD957X_VOUTL1,
0013     BD957X_VOUTS1,
0014 };
0015
0016 /*
0017  * The BD9576 has own IRQ 'blocks' for:
0018  *  - I2C/thermal,
0019  *  - Over voltage protection
0020  *  - Short-circuit protection
0021  *  - Over current protection
0022  *  - Over voltage detection
0023  *  - Under voltage detection
0024  *  - Under voltage protection
0025  *  - 'system interrupt'.
0026  *
0027  * Each of the blocks have a status register giving more accurate IRQ source
0028  * information - for example which of the regulators have over-voltage.
0029  *
0030  * On top of this, there is "main IRQ" status register where each bit indicates
0031  * which of sub-blocks have active IRQs. Fine. That would fit regmap-irq main
0032  * status handling. Except that:
0033  *  - Only some sub-IRQs can be masked.
0034  *  - The IRQ informs us about fault-condition, not when fault state changes.
0035  *    The IRQ line it is kept asserted until the detected condition is acked
0036  *    AND cleared in HW. This is annoying for IRQs like the one informing high
0037  *    temperature because if IRQ is not disabled it keeps the CPU in IRQ
0038  *    handling loop.
0039  *
0040  * For now we do just use the main-IRQ register as source for our IRQ
0041  * information and bind the regmap-irq to this. We leave fine-grained sub-IRQ
0042  * register handling to handlers in sub-devices. The regulator driver shall
0043  * read which regulators are source for problem - or if the detected error is
0044  * regulator temperature error. The sub-drivers do also handle masking of "sub-
0045  * IRQs" if this is supported/needed.
0046  *
0047  * To overcome the problem with HW keeping IRQ asserted we do call
0048  * disable_irq_nosync() from sub-device handler and add a delayed work to
0049  * re-enable IRQ roughly 1 second later. This should keep our CPU out of
0050  * busy-loop.
0051  */
0052 #define IRQS_SILENT_MS          1000
0053
0054 enum {
0055     BD9576_INT_THERM,
0056     BD9576_INT_OVP,
0057     BD9576_INT_SCP,
0058     BD9576_INT_OCP,
0059     BD9576_INT_OVD,
0060     BD9576_INT_UVD,
0061     BD9576_INT_UVP,
0062     BD9576_INT_SYS,
0063 };
0064
0065 #define BD957X_REG_SMRB_ASSERT      0x15
0066 #define BD957X_REG_PMIC_INTERNAL_STAT   0x20
0067 #define BD957X_REG_INT_THERM_STAT   0x23
0068 #define BD957X_REG_INT_THERM_MASK   0x24
0069 #define BD957X_REG_INT_OVP_STAT     0x25
0070 #define BD957X_REG_INT_SCP_STAT     0x26
0071 #define BD957X_REG_INT_OCP_STAT     0x27
0072 #define BD957X_REG_INT_OVD_STAT     0x28
0073 #define BD957X_REG_INT_UVD_STAT     0x29
0074 #define BD957X_REG_INT_UVP_STAT     0x2a
0075 #define BD957X_REG_INT_SYS_STAT     0x2b
0076 #define BD957X_REG_INT_SYS_MASK     0x2c
0077 #define BD957X_REG_INT_MAIN_STAT    0x30
0078 #define BD957X_REG_INT_MAIN_MASK    0x31
0079
0080 #define UVD_IRQ_VALID_MASK      0x6F
0081 #define OVD_IRQ_VALID_MASK      0x2F
0082
0083 #define BD957X_MASK_INT_MAIN_THERM  BIT(0)
0084 #define BD957X_MASK_INT_MAIN_OVP    BIT(1)
0085 #define BD957X_MASK_INT_MAIN_SCP    BIT(2)
0086 #define BD957X_MASK_INT_MAIN_OCP    BIT(3)
0087 #define BD957X_MASK_INT_MAIN_OVD    BIT(4)
0088 #define BD957X_MASK_INT_MAIN_UVD    BIT(5)
0089 #define BD957X_MASK_INT_MAIN_UVP    BIT(6)
0090 #define BD957X_MASK_INT_MAIN_SYS    BIT(7)
0091 #define BD957X_MASK_INT_ALL     0xff
0092
0093 #define BD957X_REG_WDT_CONF     0x16
0094
0095 #define BD957X_REG_POW_TRIGGER1     0x41
0096 #define BD957X_REG_POW_TRIGGER2     0x42
0097 #define BD957X_REG_POW_TRIGGER3     0x43
0098 #define BD957X_REG_POW_TRIGGER4     0x44
0099 #define BD957X_REG_POW_TRIGGERL1    0x45
0100 #define BD957X_REG_POW_TRIGGERS1    0x46
0101
0102 #define BD957X_REGULATOR_EN_MASK    0xff
0103 #define BD957X_REGULATOR_DIS_VAL    0xff
0104
0105 #define BD957X_VSEL_REG_MASK        0xff
0106
0107 #define BD957X_MASK_VOUT1_TUNE      0x87
0108 #define BD957X_MASK_VOUT2_TUNE      0x87
0109 #define BD957X_MASK_VOUT3_TUNE      0x1f
0110 #define BD957X_MASK_VOUT4_TUNE      0x1f
0111 #define BD957X_MASK_VOUTL1_TUNE     0x87
0112
0113 #define BD957X_REG_VOUT1_TUNE       0x50
0114 #define BD957X_REG_VOUT2_TUNE       0x53
0115 #define BD957X_REG_VOUT3_TUNE       0x56
0116 #define BD957X_REG_VOUT4_TUNE       0x59
0117 #define BD957X_REG_VOUTL1_TUNE      0x5c
0118
0119 #define BD9576_REG_VOUT1_OVD        0x51
0120 #define BD9576_REG_VOUT1_UVD        0x52
0121 #define BD9576_REG_VOUT2_OVD        0x54
0122 #define BD9576_REG_VOUT2_UVD        0x55
0123 #define BD9576_REG_VOUT3_OVD        0x57
0124 #define BD9576_REG_VOUT3_UVD        0x58
0125 #define BD9576_REG_VOUT4_OVD        0x5a
0126 #define BD9576_REG_VOUT4_UVD        0x5b
0127 #define BD9576_REG_VOUTL1_OVD       0x5d
0128 #define BD9576_REG_VOUTL1_UVD       0x5e
0129
0130 #define BD9576_MASK_XVD         0x7f
0131
0132 #define BD9576_REG_VOUT1S_OCW       0x5f
0133 #define BD9576_REG_VOUT1S_OCP       0x60
0134
0135 #define BD9576_MASK_VOUT1S_OCW      0x3f
0136 #define BD9576_MASK_VOUT1S_OCP      0x3f
0137
0138 #define BD957X_MAX_REGISTER     0x61
0139
0140 #endif