linux/mfd/rohm-bd718x7.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /* Copyright (C) 2018 ROHM Semiconductors */
0003
0004 #ifndef __LINUX_MFD_BD718XX_H__
0005 #define __LINUX_MFD_BD718XX_H__
0006
0007 #include <linux/mfd/rohm-generic.h>
0008 #include <linux/regmap.h>
0009
0010 enum {
0011     BD718XX_BUCK1 = 0,
0012     BD718XX_BUCK2,
0013     BD718XX_BUCK3,
0014     BD718XX_BUCK4,
0015     BD718XX_BUCK5,
0016     BD718XX_BUCK6,
0017     BD718XX_BUCK7,
0018     BD718XX_BUCK8,
0019     BD718XX_LDO1,
0020     BD718XX_LDO2,
0021     BD718XX_LDO3,
0022     BD718XX_LDO4,
0023     BD718XX_LDO5,
0024     BD718XX_LDO6,
0025     BD718XX_LDO7,
0026     BD718XX_REGULATOR_AMOUNT,
0027 };
0028
0029 /* Common voltage configurations */
0030 #define BD718XX_DVS_BUCK_VOLTAGE_NUM        0x3D
0031 #define BD718XX_4TH_NODVS_BUCK_VOLTAGE_NUM  0x3D
0032
0033 #define BD718XX_LDO1_VOLTAGE_NUM    0x08
0034 #define BD718XX_LDO2_VOLTAGE_NUM    0x02
0035 #define BD718XX_LDO3_VOLTAGE_NUM    0x10
0036 #define BD718XX_LDO4_VOLTAGE_NUM    0x0A
0037 #define BD718XX_LDO6_VOLTAGE_NUM    0x0A
0038
0039 /* BD71837 specific voltage configurations */
0040 #define BD71837_BUCK5_VOLTAGE_NUM   0x10
0041 #define BD71837_BUCK6_VOLTAGE_NUM   0x04
0042 #define BD71837_BUCK7_VOLTAGE_NUM   0x08
0043 #define BD71837_LDO5_VOLTAGE_NUM    0x10
0044 #define BD71837_LDO7_VOLTAGE_NUM    0x10
0045
0046 /* BD71847 specific voltage configurations */
0047 #define BD71847_BUCK3_VOLTAGE_NUM   0x18
0048 #define BD71847_BUCK4_VOLTAGE_NUM   0x08
0049 #define BD71847_LDO5_VOLTAGE_NUM    0x20
0050
0051 /* Registers specific to BD71837 */
0052 enum {
0053     BD71837_REG_BUCK3_CTRL =    0x07,
0054     BD71837_REG_BUCK4_CTRL =    0x08,
0055     BD71837_REG_BUCK3_VOLT_RUN =    0x12,
0056     BD71837_REG_BUCK4_VOLT_RUN =    0x13,
0057     BD71837_REG_LDO7_VOLT =     0x1E,
0058 };
0059
0060 /* Registers common for BD71837 and BD71847 */
0061 enum {
0062     BD718XX_REG_REV =           0x00,
0063     BD718XX_REG_SWRESET =           0x01,
0064     BD718XX_REG_I2C_DEV =           0x02,
0065     BD718XX_REG_PWRCTRL0 =          0x03,
0066     BD718XX_REG_PWRCTRL1 =          0x04,
0067     BD718XX_REG_BUCK1_CTRL =        0x05,
0068     BD718XX_REG_BUCK2_CTRL =        0x06,
0069     BD718XX_REG_1ST_NODVS_BUCK_CTRL =   0x09,
0070     BD718XX_REG_2ND_NODVS_BUCK_CTRL =   0x0A,
0071     BD718XX_REG_3RD_NODVS_BUCK_CTRL =   0x0B,
0072     BD718XX_REG_4TH_NODVS_BUCK_CTRL =   0x0C,
0073     BD718XX_REG_BUCK1_VOLT_RUN =        0x0D,
0074     BD718XX_REG_BUCK1_VOLT_IDLE =       0x0E,
0075     BD718XX_REG_BUCK1_VOLT_SUSP =       0x0F,
0076     BD718XX_REG_BUCK2_VOLT_RUN =        0x10,
0077     BD718XX_REG_BUCK2_VOLT_IDLE =       0x11,
0078     BD718XX_REG_1ST_NODVS_BUCK_VOLT =   0x14,
0079     BD718XX_REG_2ND_NODVS_BUCK_VOLT =   0x15,
0080     BD718XX_REG_3RD_NODVS_BUCK_VOLT =   0x16,
0081     BD718XX_REG_4TH_NODVS_BUCK_VOLT =   0x17,
0082     BD718XX_REG_LDO1_VOLT =         0x18,
0083     BD718XX_REG_LDO2_VOLT =         0x19,
0084     BD718XX_REG_LDO3_VOLT =         0x1A,
0085     BD718XX_REG_LDO4_VOLT =         0x1B,
0086     BD718XX_REG_LDO5_VOLT =         0x1C,
0087     BD718XX_REG_LDO6_VOLT =         0x1D,
0088     BD718XX_REG_TRANS_COND0 =       0x1F,
0089     BD718XX_REG_TRANS_COND1 =       0x20,
0090     BD718XX_REG_VRFAULTEN =         0x21,
0091     BD718XX_REG_MVRFLTMASK0 =       0x22,
0092     BD718XX_REG_MVRFLTMASK1 =       0x23,
0093     BD718XX_REG_MVRFLTMASK2 =       0x24,
0094     BD718XX_REG_RCVCFG =            0x25,
0095     BD718XX_REG_RCVNUM =            0x26,
0096     BD718XX_REG_PWRONCONFIG0 =      0x27,
0097     BD718XX_REG_PWRONCONFIG1 =      0x28,
0098     BD718XX_REG_RESETSRC =          0x29,
0099     BD718XX_REG_MIRQ =          0x2A,
0100     BD718XX_REG_IRQ =           0x2B,
0101     BD718XX_REG_IN_MON =            0x2C,
0102     BD718XX_REG_POW_STATE =         0x2D,
0103     BD718XX_REG_OUT32K =            0x2E,
0104     BD718XX_REG_REGLOCK =           0x2F,
0105     BD718XX_REG_OTPVER =            0xFF,
0106     BD718XX_MAX_REGISTER =          0x100,
0107 };
0108
0109 #define REGLOCK_PWRSEQ  0x1
0110 #define REGLOCK_VREG    0x10
0111
0112 /* Generic BUCK control masks */
0113 #define BD718XX_BUCK_SEL    0x02
0114 #define BD718XX_BUCK_EN     0x01
0115 #define BD718XX_BUCK_RUN_ON 0x04
0116
0117 /* Generic LDO masks */
0118 #define BD718XX_LDO_SEL     0x80
0119 #define BD718XX_LDO_EN      0x40
0120
0121 /* BD71837 BUCK ramp rate CTRL reg bits */
0122 #define BUCK_RAMPRATE_MASK  0xC0
0123 #define BUCK_RAMPRATE_10P00MV   0x0
0124 #define BUCK_RAMPRATE_5P00MV    0x1
0125 #define BUCK_RAMPRATE_2P50MV    0x2
0126 #define BUCK_RAMPRATE_1P25MV    0x3
0127
0128 #define DVS_BUCK_RUN_MASK   0x3F
0129 #define DVS_BUCK_SUSP_MASK  0x3F
0130 #define DVS_BUCK_IDLE_MASK  0x3F
0131
0132 #define BD718XX_1ST_NODVS_BUCK_MASK 0x07
0133 #define BD718XX_3RD_NODVS_BUCK_MASK 0x07
0134 #define BD718XX_4TH_NODVS_BUCK_MASK 0x3F
0135
0136 #define BD71847_BUCK3_MASK      0x07
0137 #define BD71847_BUCK3_RANGE_MASK    0xC0
0138 #define BD71847_BUCK4_MASK      0x03
0139 #define BD71847_BUCK4_RANGE_MASK    0x40
0140
0141 #define BD71837_BUCK5_MASK      0x07
0142 #define BD71837_BUCK5_RANGE_MASK    0x80
0143 #define BD71837_BUCK6_MASK      0x03
0144
0145 #define BD718XX_LDO1_MASK       0x03
0146 #define BD718XX_LDO1_RANGE_MASK     0x20
0147 #define BD718XX_LDO2_MASK       0x20
0148 #define BD718XX_LDO3_MASK       0x0F
0149 #define BD718XX_LDO4_MASK       0x0F
0150 #define BD718XX_LDO6_MASK       0x0F
0151
0152 #define BD71837_LDO5_MASK       0x0F
0153 #define BD71847_LDO5_MASK       0x0F
0154 #define BD71847_LDO5_RANGE_MASK     0x20
0155
0156 #define BD71837_LDO7_MASK       0x0F
0157
0158 /* BD718XX Voltage monitoring masks */
0159 #define BD718XX_BUCK1_VRMON80           0x1
0160 #define BD718XX_BUCK1_VRMON130          0x2
0161 #define BD718XX_BUCK2_VRMON80           0x4
0162 #define BD718XX_BUCK2_VRMON130          0x8
0163 #define BD718XX_1ST_NODVS_BUCK_VRMON80  0x1
0164 #define BD718XX_1ST_NODVS_BUCK_VRMON130 0x2
0165 #define BD718XX_2ND_NODVS_BUCK_VRMON80  0x4
0166 #define BD718XX_2ND_NODVS_BUCK_VRMON130 0x8
0167 #define BD718XX_3RD_NODVS_BUCK_VRMON80  0x10
0168 #define BD718XX_3RD_NODVS_BUCK_VRMON130 0x20
0169 #define BD718XX_4TH_NODVS_BUCK_VRMON80  0x40
0170 #define BD718XX_4TH_NODVS_BUCK_VRMON130 0x80
0171 #define BD718XX_LDO1_VRMON80            0x1
0172 #define BD718XX_LDO2_VRMON80            0x2
0173 #define BD718XX_LDO3_VRMON80            0x4
0174 #define BD718XX_LDO4_VRMON80            0x8
0175 #define BD718XX_LDO5_VRMON80            0x10
0176 #define BD718XX_LDO6_VRMON80            0x20
0177
0178 /* BD71837 specific voltage monitoring masks */
0179 #define BD71837_BUCK3_VRMON80           0x10
0180 #define BD71837_BUCK3_VRMON130          0x20
0181 #define BD71837_BUCK4_VRMON80           0x40
0182 #define BD71837_BUCK4_VRMON130          0x80
0183 #define BD71837_LDO7_VRMON80            0x40
0184
0185 /* BD718XX_REG_IRQ bits */
0186 #define IRQ_SWRST       0x40
0187 #define IRQ_PWRON_S     0x20
0188 #define IRQ_PWRON_L     0x10
0189 #define IRQ_PWRON       0x08
0190 #define IRQ_WDOG        0x04
0191 #define IRQ_ON_REQ      0x02
0192 #define IRQ_STBY_REQ        0x01
0193
0194 /* ROHM BD718XX irqs */
0195 enum {
0196     BD718XX_INT_STBY_REQ,
0197     BD718XX_INT_ON_REQ,
0198     BD718XX_INT_WDOG,
0199     BD718XX_INT_PWRBTN,
0200     BD718XX_INT_PWRBTN_L,
0201     BD718XX_INT_PWRBTN_S,
0202     BD718XX_INT_SWRST
0203 };
0204
0205 /* ROHM BD718XX interrupt masks */
0206 #define BD718XX_INT_SWRST_MASK      0x40
0207 #define BD718XX_INT_PWRBTN_S_MASK   0x20
0208 #define BD718XX_INT_PWRBTN_L_MASK   0x10
0209 #define BD718XX_INT_PWRBTN_MASK     0x8
0210 #define BD718XX_INT_WDOG_MASK       0x4
0211 #define BD718XX_INT_ON_REQ_MASK     0x2
0212 #define BD718XX_INT_STBY_REQ_MASK   0x1
0213
0214 /* Register write induced reset settings */
0215
0216 /*
0217  * Even though the bit zero is not SWRESET type we still want to write zero
0218  * to it when changing type. Bit zero is 'SWRESET' trigger bit and if we
0219  * write 1 to it we will trigger the action. So always write 0 to it when
0220  * changning SWRESET action - no matter what we read from it.
0221  */
0222 #define BD718XX_SWRESET_TYPE_MASK   7
0223 #define BD718XX_SWRESET_TYPE_DISABLED   0
0224 #define BD718XX_SWRESET_TYPE_COLD   4
0225 #define BD718XX_SWRESET_TYPE_WARM   6
0226
0227 #define BD718XX_SWRESET_RESET_MASK  1
0228 #define BD718XX_SWRESET_RESET       1
0229
0230 /* Poweroff state transition conditions */
0231
0232 #define BD718XX_ON_REQ_POWEROFF_MASK    1
0233 #define BD718XX_SWRESET_POWEROFF_MASK   2
0234 #define BD718XX_WDOG_POWEROFF_MASK  4
0235 #define BD718XX_KEY_L_POWEROFF_MASK 8
0236
0237 #define BD718XX_POWOFF_TO_SNVS  0
0238 #define BD718XX_POWOFF_TO_RDY   0xF
0239
0240 #define BD718XX_POWOFF_TIME_MASK 0xF0
0241 enum {
0242     BD718XX_POWOFF_TIME_5MS = 0,
0243     BD718XX_POWOFF_TIME_10MS,
0244     BD718XX_POWOFF_TIME_15MS,
0245     BD718XX_POWOFF_TIME_20MS,
0246     BD718XX_POWOFF_TIME_25MS,
0247     BD718XX_POWOFF_TIME_30MS,
0248     BD718XX_POWOFF_TIME_35MS,
0249     BD718XX_POWOFF_TIME_40MS,
0250     BD718XX_POWOFF_TIME_45MS,
0251     BD718XX_POWOFF_TIME_50MS,
0252     BD718XX_POWOFF_TIME_75MS,
0253     BD718XX_POWOFF_TIME_100MS,
0254     BD718XX_POWOFF_TIME_250MS,
0255     BD718XX_POWOFF_TIME_500MS,
0256     BD718XX_POWOFF_TIME_750MS,
0257     BD718XX_POWOFF_TIME_1500MS
0258 };
0259
0260 /* Poweron sequence state transition conditions */
0261 #define BD718XX_RDY_TO_SNVS_MASK 0xF
0262 #define BD718XX_SNVS_TO_RUN_MASK 0xF0
0263
0264 #define BD718XX_PWR_TRIG_KEY_L      1
0265 #define BD718XX_PWR_TRIG_KEY_S      2
0266 #define BD718XX_PWR_TRIG_PMIC_ON    4
0267 #define BD718XX_PWR_TRIG_VSYS_UVLO  8
0268 #define BD718XX_RDY_TO_SNVS_SIFT    0
0269 #define BD718XX_SNVS_TO_RUN_SIFT    4
0270
0271 #define BD718XX_PWRBTN_PRESS_DURATION_MASK 0xF
0272
0273 /* Timeout value for detecting short press */
0274 enum {
0275     BD718XX_PWRBTN_SHORT_PRESS_10MS = 0,
0276     BD718XX_PWRBTN_SHORT_PRESS_500MS,
0277     BD718XX_PWRBTN_SHORT_PRESS_1000MS,
0278     BD718XX_PWRBTN_SHORT_PRESS_1500MS,
0279     BD718XX_PWRBTN_SHORT_PRESS_2000MS,
0280     BD718XX_PWRBTN_SHORT_PRESS_2500MS,
0281     BD718XX_PWRBTN_SHORT_PRESS_3000MS,
0282     BD718XX_PWRBTN_SHORT_PRESS_3500MS,
0283     BD718XX_PWRBTN_SHORT_PRESS_4000MS,
0284     BD718XX_PWRBTN_SHORT_PRESS_4500MS,
0285     BD718XX_PWRBTN_SHORT_PRESS_5000MS,
0286     BD718XX_PWRBTN_SHORT_PRESS_5500MS,
0287     BD718XX_PWRBTN_SHORT_PRESS_6000MS,
0288     BD718XX_PWRBTN_SHORT_PRESS_6500MS,
0289     BD718XX_PWRBTN_SHORT_PRESS_7000MS,
0290     BD718XX_PWRBTN_SHORT_PRESS_7500MS
0291 };
0292
0293 /* Timeout value for detecting LONG press */
0294 enum {
0295     BD718XX_PWRBTN_LONG_PRESS_10MS = 0,
0296     BD718XX_PWRBTN_LONG_PRESS_1S,
0297     BD718XX_PWRBTN_LONG_PRESS_2S,
0298     BD718XX_PWRBTN_LONG_PRESS_3S,
0299     BD718XX_PWRBTN_LONG_PRESS_4S,
0300     BD718XX_PWRBTN_LONG_PRESS_5S,
0301     BD718XX_PWRBTN_LONG_PRESS_6S,
0302     BD718XX_PWRBTN_LONG_PRESS_7S,
0303     BD718XX_PWRBTN_LONG_PRESS_8S,
0304     BD718XX_PWRBTN_LONG_PRESS_9S,
0305     BD718XX_PWRBTN_LONG_PRESS_10S,
0306     BD718XX_PWRBTN_LONG_PRESS_11S,
0307     BD718XX_PWRBTN_LONG_PRESS_12S,
0308     BD718XX_PWRBTN_LONG_PRESS_13S,
0309     BD718XX_PWRBTN_LONG_PRESS_14S,
0310     BD718XX_PWRBTN_LONG_PRESS_15S
0311 };
0312
0313 #endif /* __LINUX_MFD_BD718XX_H__ */