linux/mfd/rohm-bd71828.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /* Copyright (C) 2019 ROHM Semiconductors */
0003
0004 #ifndef __LINUX_MFD_BD71828_H__
0005 #define __LINUX_MFD_BD71828_H__
0006
0007 #include <linux/mfd/rohm-generic.h>
0008 #include <linux/mfd/rohm-shared.h>
0009
0010 /* Regulator IDs */
0011 enum {
0012     BD71828_BUCK1,
0013     BD71828_BUCK2,
0014     BD71828_BUCK3,
0015     BD71828_BUCK4,
0016     BD71828_BUCK5,
0017     BD71828_BUCK6,
0018     BD71828_BUCK7,
0019     BD71828_LDO1,
0020     BD71828_LDO2,
0021     BD71828_LDO3,
0022     BD71828_LDO4,
0023     BD71828_LDO5,
0024     BD71828_LDO6,
0025     BD71828_LDO_SNVS,
0026     BD71828_REGULATOR_AMOUNT,
0027 };
0028
0029 #define BD71828_BUCK1267_VOLTS      0x100
0030 #define BD71828_BUCK3_VOLTS     0x20
0031 #define BD71828_BUCK4_VOLTS     0x40
0032 #define BD71828_BUCK5_VOLTS     0x20
0033 #define BD71828_LDO_VOLTS       0x40
0034 /* LDO6 is fixed 1.8V voltage */
0035 #define BD71828_LDO_6_VOLTAGE       1800000
0036
0037 /* Registers and masks*/
0038
0039 /* MODE control */
0040 #define BD71828_REG_PS_CTRL_1       0x04
0041 #define BD71828_REG_PS_CTRL_2       0x05
0042 #define BD71828_REG_PS_CTRL_3       0x06
0043
0044 //#define BD71828_REG_SWRESET       0x06
0045 #define BD71828_MASK_RUN_LVL_CTRL   0x30
0046
0047 /* Regulator control masks */
0048
0049 #define BD71828_MASK_RAMP_DELAY     0x6
0050
0051 #define BD71828_MASK_RUN_EN     0x08
0052 #define BD71828_MASK_SUSP_EN        0x04
0053 #define BD71828_MASK_IDLE_EN        0x02
0054 #define BD71828_MASK_LPSR_EN        0x01
0055
0056 #define BD71828_MASK_RUN0_EN        0x01
0057 #define BD71828_MASK_RUN1_EN        0x02
0058 #define BD71828_MASK_RUN2_EN        0x04
0059 #define BD71828_MASK_RUN3_EN        0x08
0060
0061 #define BD71828_MASK_DVS_BUCK1_CTRL 0x10
0062 #define BD71828_DVS_BUCK1_CTRL_I2C  0
0063 #define BD71828_DVS_BUCK1_USE_RUNLVL    0x10
0064
0065 #define BD71828_MASK_DVS_BUCK2_CTRL 0x20
0066 #define BD71828_DVS_BUCK2_CTRL_I2C  0
0067 #define BD71828_DVS_BUCK2_USE_RUNLVL    0x20
0068
0069 #define BD71828_MASK_DVS_BUCK6_CTRL 0x40
0070 #define BD71828_DVS_BUCK6_CTRL_I2C  0
0071 #define BD71828_DVS_BUCK6_USE_RUNLVL    0x40
0072
0073 #define BD71828_MASK_DVS_BUCK7_CTRL 0x80
0074 #define BD71828_DVS_BUCK7_CTRL_I2C  0
0075 #define BD71828_DVS_BUCK7_USE_RUNLVL    0x80
0076
0077 #define BD71828_MASK_BUCK1267_VOLT  0xff
0078 #define BD71828_MASK_BUCK3_VOLT     0x1f
0079 #define BD71828_MASK_BUCK4_VOLT     0x3f
0080 #define BD71828_MASK_BUCK5_VOLT     0x1f
0081 #define BD71828_MASK_LDO_VOLT       0x3f
0082
0083 /* Regulator control regs */
0084 #define BD71828_REG_BUCK1_EN        0x08
0085 #define BD71828_REG_BUCK1_CTRL      0x09
0086 #define BD71828_REG_BUCK1_MODE      0x0a
0087 #define BD71828_REG_BUCK1_IDLE_VOLT 0x0b
0088 #define BD71828_REG_BUCK1_SUSP_VOLT 0x0c
0089 #define BD71828_REG_BUCK1_VOLT      0x0d
0090
0091 #define BD71828_REG_BUCK2_EN        0x12
0092 #define BD71828_REG_BUCK2_CTRL      0x13
0093 #define BD71828_REG_BUCK2_MODE      0x14
0094 #define BD71828_REG_BUCK2_IDLE_VOLT 0x15
0095 #define BD71828_REG_BUCK2_SUSP_VOLT 0x16
0096 #define BD71828_REG_BUCK2_VOLT      0x17
0097
0098 #define BD71828_REG_BUCK3_EN        0x1c
0099 #define BD71828_REG_BUCK3_MODE      0x1d
0100 #define BD71828_REG_BUCK3_VOLT      0x1e
0101
0102 #define BD71828_REG_BUCK4_EN        0x1f
0103 #define BD71828_REG_BUCK4_MODE      0x20
0104 #define BD71828_REG_BUCK4_VOLT      0x21
0105
0106 #define BD71828_REG_BUCK5_EN        0x22
0107 #define BD71828_REG_BUCK5_MODE      0x23
0108 #define BD71828_REG_BUCK5_VOLT      0x24
0109
0110 #define BD71828_REG_BUCK6_EN        0x25
0111 #define BD71828_REG_BUCK6_CTRL      0x26
0112 #define BD71828_REG_BUCK6_MODE      0x27
0113 #define BD71828_REG_BUCK6_IDLE_VOLT 0x28
0114 #define BD71828_REG_BUCK6_SUSP_VOLT 0x29
0115 #define BD71828_REG_BUCK6_VOLT      0x2a
0116
0117 #define BD71828_REG_BUCK7_EN        0x2f
0118 #define BD71828_REG_BUCK7_CTRL      0x30
0119 #define BD71828_REG_BUCK7_MODE      0x31
0120 #define BD71828_REG_BUCK7_IDLE_VOLT 0x32
0121 #define BD71828_REG_BUCK7_SUSP_VOLT 0x33
0122 #define BD71828_REG_BUCK7_VOLT      0x34
0123
0124 #define BD71828_REG_LDO1_EN     0x39
0125 #define BD71828_REG_LDO1_VOLT       0x3a
0126 #define BD71828_REG_LDO2_EN     0x3b
0127 #define BD71828_REG_LDO2_VOLT       0x3c
0128 #define BD71828_REG_LDO3_EN     0x3d
0129 #define BD71828_REG_LDO3_VOLT       0x3e
0130 #define BD71828_REG_LDO4_EN     0x3f
0131 #define BD71828_REG_LDO4_VOLT       0x40
0132 #define BD71828_REG_LDO5_EN     0x41
0133 #define BD71828_REG_LDO5_VOLT       0x43
0134 #define BD71828_REG_LDO5_VOLT_OPT   0x42
0135 #define BD71828_REG_LDO6_EN     0x44
0136 //#define BD71828_REG_LDO6_VOLT     0x4
0137 #define BD71828_REG_LDO7_EN     0x45
0138 #define BD71828_REG_LDO7_VOLT       0x46
0139
0140 /* GPIO */
0141
0142 #define BD71828_GPIO_DRIVE_MASK     0x2
0143 #define BD71828_GPIO_OPEN_DRAIN     0x0
0144 #define BD71828_GPIO_PUSH_PULL      0x2
0145 #define BD71828_GPIO_OUT_HI     0x1
0146 #define BD71828_GPIO_OUT_LO     0x0
0147 #define BD71828_GPIO_OUT_MASK       0x1
0148
0149 #define BD71828_REG_GPIO_CTRL1      0x47
0150 #define BD71828_REG_GPIO_CTRL2      0x48
0151 #define BD71828_REG_GPIO_CTRL3      0x49
0152 #define BD71828_REG_IO_STAT     0xed
0153
0154 /* clk */
0155 #define BD71828_REG_OUT32K      0x4b
0156
0157 /* RTC */
0158 #define BD71828_REG_RTC_SEC     0x4c
0159 #define BD71828_REG_RTC_MINUTE      0x4d
0160 #define BD71828_REG_RTC_HOUR        0x4e
0161 #define BD71828_REG_RTC_WEEK        0x4f
0162 #define BD71828_REG_RTC_DAY     0x50
0163 #define BD71828_REG_RTC_MONTH       0x51
0164 #define BD71828_REG_RTC_YEAR        0x52
0165
0166 #define BD71828_REG_RTC_ALM0_SEC    0x53
0167 #define BD71828_REG_RTC_ALM_START   BD71828_REG_RTC_ALM0_SEC
0168 #define BD71828_REG_RTC_ALM0_MINUTE 0x54
0169 #define BD71828_REG_RTC_ALM0_HOUR   0x55
0170 #define BD71828_REG_RTC_ALM0_WEEK   0x56
0171 #define BD71828_REG_RTC_ALM0_DAY    0x57
0172 #define BD71828_REG_RTC_ALM0_MONTH  0x58
0173 #define BD71828_REG_RTC_ALM0_YEAR   0x59
0174 #define BD71828_REG_RTC_ALM0_MASK   0x61
0175
0176 #define BD71828_REG_RTC_ALM1_SEC    0x5a
0177 #define BD71828_REG_RTC_ALM1_MINUTE 0x5b
0178 #define BD71828_REG_RTC_ALM1_HOUR   0x5c
0179 #define BD71828_REG_RTC_ALM1_WEEK   0x5d
0180 #define BD71828_REG_RTC_ALM1_DAY    0x5e
0181 #define BD71828_REG_RTC_ALM1_MONTH  0x5f
0182 #define BD71828_REG_RTC_ALM1_YEAR   0x60
0183 #define BD71828_REG_RTC_ALM1_MASK   0x62
0184
0185 #define BD71828_REG_RTC_ALM2        0x63
0186 #define BD71828_REG_RTC_START       BD71828_REG_RTC_SEC
0187
0188 /* Charger/Battey */
0189 #define BD71828_REG_CHG_STATE       0x65
0190 #define BD71828_REG_CHG_FULL        0xd2
0191
0192 /* LEDs */
0193 #define BD71828_REG_LED_CTRL        0x4A
0194 #define BD71828_MASK_LED_AMBER      0x80
0195 #define BD71828_MASK_LED_GREEN      0x40
0196 #define BD71828_LED_ON          0xff
0197 #define BD71828_LED_OFF         0x0
0198
0199 /* IRQ registers */
0200 #define BD71828_REG_INT_MASK_BUCK   0xd3
0201 #define BD71828_REG_INT_MASK_DCIN1  0xd4
0202 #define BD71828_REG_INT_MASK_DCIN2  0xd5
0203 #define BD71828_REG_INT_MASK_VSYS   0xd6
0204 #define BD71828_REG_INT_MASK_CHG    0xd7
0205 #define BD71828_REG_INT_MASK_BAT    0xd8
0206 #define BD71828_REG_INT_MASK_BAT_MON1   0xd9
0207 #define BD71828_REG_INT_MASK_BAT_MON2   0xda
0208 #define BD71828_REG_INT_MASK_BAT_MON3   0xdb
0209 #define BD71828_REG_INT_MASK_BAT_MON4   0xdc
0210 #define BD71828_REG_INT_MASK_TEMP   0xdd
0211 #define BD71828_REG_INT_MASK_RTC    0xde
0212
0213 #define BD71828_REG_INT_MAIN        0xdf
0214 #define BD71828_REG_INT_BUCK        0xe0
0215 #define BD71828_REG_INT_DCIN1       0xe1
0216 #define BD71828_REG_INT_DCIN2       0xe2
0217 #define BD71828_REG_INT_VSYS        0xe3
0218 #define BD71828_REG_INT_CHG     0xe4
0219 #define BD71828_REG_INT_BAT     0xe5
0220 #define BD71828_REG_INT_BAT_MON1    0xe6
0221 #define BD71828_REG_INT_BAT_MON2    0xe7
0222 #define BD71828_REG_INT_BAT_MON3    0xe8
0223 #define BD71828_REG_INT_BAT_MON4    0xe9
0224 #define BD71828_REG_INT_TEMP        0xea
0225 #define BD71828_REG_INT_RTC     0xeb
0226 #define BD71828_REG_INT_UPDATE      0xec
0227
0228 #define BD71828_MAX_REGISTER BD71828_REG_IO_STAT
0229
0230 /* Masks for main IRQ register bits */
0231 enum {
0232     BD71828_INT_BUCK,
0233 #define BD71828_INT_BUCK_MASK BIT(BD71828_INT_BUCK)
0234     BD71828_INT_DCIN,
0235 #define BD71828_INT_DCIN_MASK BIT(BD71828_INT_DCIN)
0236     BD71828_INT_VSYS,
0237 #define BD71828_INT_VSYS_MASK BIT(BD71828_INT_VSYS)
0238     BD71828_INT_CHG,
0239 #define BD71828_INT_CHG_MASK BIT(BD71828_INT_CHG)
0240     BD71828_INT_BAT,
0241 #define BD71828_INT_BAT_MASK BIT(BD71828_INT_BAT)
0242     BD71828_INT_BAT_MON,
0243 #define BD71828_INT_BAT_MON_MASK BIT(BD71828_INT_BAT_MON)
0244     BD71828_INT_TEMP,
0245 #define BD71828_INT_TEMP_MASK BIT(BD71828_INT_TEMP)
0246     BD71828_INT_RTC,
0247 #define BD71828_INT_RTC_MASK BIT(BD71828_INT_RTC)
0248 };
0249
0250 /* Interrupts */
0251 enum {
0252     /* BUCK reg interrupts */
0253     BD71828_INT_BUCK1_OCP,
0254     BD71828_INT_BUCK2_OCP,
0255     BD71828_INT_BUCK3_OCP,
0256     BD71828_INT_BUCK4_OCP,
0257     BD71828_INT_BUCK5_OCP,
0258     BD71828_INT_BUCK6_OCP,
0259     BD71828_INT_BUCK7_OCP,
0260     BD71828_INT_PGFAULT,
0261     /* DCIN1 interrupts */
0262     BD71828_INT_DCIN_DET,
0263     BD71828_INT_DCIN_RMV,
0264     BD71828_INT_CLPS_OUT,
0265     BD71828_INT_CLPS_IN,
0266     /* DCIN2 interrupts */
0267     BD71828_INT_DCIN_MON_RES,
0268     BD71828_INT_DCIN_MON_DET,
0269     BD71828_INT_LONGPUSH,
0270     BD71828_INT_MIDPUSH,
0271     BD71828_INT_SHORTPUSH,
0272     BD71828_INT_PUSH,
0273     BD71828_INT_WDOG,
0274     BD71828_INT_SWRESET,
0275     /* Vsys */
0276     BD71828_INT_VSYS_UV_RES,
0277     BD71828_INT_VSYS_UV_DET,
0278     BD71828_INT_VSYS_LOW_RES,
0279     BD71828_INT_VSYS_LOW_DET,
0280     BD71828_INT_VSYS_HALL_IN,
0281     BD71828_INT_VSYS_HALL_TOGGLE,
0282     BD71828_INT_VSYS_MON_RES,
0283     BD71828_INT_VSYS_MON_DET,
0284     /* Charger */
0285     BD71828_INT_CHG_DCIN_ILIM,
0286     BD71828_INT_CHG_TOPOFF_TO_DONE,
0287     BD71828_INT_CHG_WDG_TEMP,
0288     BD71828_INT_CHG_WDG_TIME,
0289     BD71828_INT_CHG_RECHARGE_RES,
0290     BD71828_INT_CHG_RECHARGE_DET,
0291     BD71828_INT_CHG_RANGED_TEMP_TRANSITION,
0292     BD71828_INT_CHG_STATE_TRANSITION,
0293     /* Battery */
0294     BD71828_INT_BAT_TEMP_NORMAL,
0295     BD71828_INT_BAT_TEMP_ERANGE,
0296     BD71828_INT_BAT_TEMP_WARN,
0297     BD71828_INT_BAT_REMOVED,
0298     BD71828_INT_BAT_DETECTED,
0299     BD71828_INT_THERM_REMOVED,
0300     BD71828_INT_THERM_DETECTED,
0301     /* Battery Mon 1 */
0302     BD71828_INT_BAT_DEAD,
0303     BD71828_INT_BAT_SHORTC_RES,
0304     BD71828_INT_BAT_SHORTC_DET,
0305     BD71828_INT_BAT_LOW_VOLT_RES,
0306     BD71828_INT_BAT_LOW_VOLT_DET,
0307     BD71828_INT_BAT_OVER_VOLT_RES,
0308     BD71828_INT_BAT_OVER_VOLT_DET,
0309     /* Battery Mon 2 */
0310     BD71828_INT_BAT_MON_RES,
0311     BD71828_INT_BAT_MON_DET,
0312     /* Battery Mon 3 (Coulomb counter) */
0313     BD71828_INT_BAT_CC_MON1,
0314     BD71828_INT_BAT_CC_MON2,
0315     BD71828_INT_BAT_CC_MON3,
0316     /* Battery Mon 4 */
0317     BD71828_INT_BAT_OVER_CURR_1_RES,
0318     BD71828_INT_BAT_OVER_CURR_1_DET,
0319     BD71828_INT_BAT_OVER_CURR_2_RES,
0320     BD71828_INT_BAT_OVER_CURR_2_DET,
0321     BD71828_INT_BAT_OVER_CURR_3_RES,
0322     BD71828_INT_BAT_OVER_CURR_3_DET,
0323     /* Temperature */
0324     BD71828_INT_TEMP_BAT_LOW_RES,
0325     BD71828_INT_TEMP_BAT_LOW_DET,
0326     BD71828_INT_TEMP_BAT_HI_RES,
0327     BD71828_INT_TEMP_BAT_HI_DET,
0328     BD71828_INT_TEMP_CHIP_OVER_125_RES,
0329     BD71828_INT_TEMP_CHIP_OVER_125_DET,
0330     BD71828_INT_TEMP_CHIP_OVER_VF_DET,
0331     BD71828_INT_TEMP_CHIP_OVER_VF_RES,
0332     /* RTC Alarm */
0333     BD71828_INT_RTC0,
0334     BD71828_INT_RTC1,
0335     BD71828_INT_RTC2,
0336 };
0337
0338 #define BD71828_INT_BUCK1_OCP_MASK          0x1
0339 #define BD71828_INT_BUCK2_OCP_MASK          0x2
0340 #define BD71828_INT_BUCK3_OCP_MASK          0x4
0341 #define BD71828_INT_BUCK4_OCP_MASK          0x8
0342 #define BD71828_INT_BUCK5_OCP_MASK          0x10
0343 #define BD71828_INT_BUCK6_OCP_MASK          0x20
0344 #define BD71828_INT_BUCK7_OCP_MASK          0x40
0345 #define BD71828_INT_PGFAULT_MASK            0x80
0346
0347 #define BD71828_INT_DCIN_DET_MASK           0x1
0348 #define BD71828_INT_DCIN_RMV_MASK           0x2
0349 #define BD71828_INT_CLPS_OUT_MASK           0x4
0350 #define BD71828_INT_CLPS_IN_MASK            0x8
0351     /* DCIN2 interrupts */
0352 #define BD71828_INT_DCIN_MON_RES_MASK           0x1
0353 #define BD71828_INT_DCIN_MON_DET_MASK           0x2
0354 #define BD71828_INT_LONGPUSH_MASK           0x4
0355 #define BD71828_INT_MIDPUSH_MASK            0x8
0356 #define BD71828_INT_SHORTPUSH_MASK          0x10
0357 #define BD71828_INT_PUSH_MASK               0x20
0358 #define BD71828_INT_WDOG_MASK               0x40
0359 #define BD71828_INT_SWRESET_MASK            0x80
0360     /* Vsys */
0361 #define BD71828_INT_VSYS_UV_RES_MASK            0x1
0362 #define BD71828_INT_VSYS_UV_DET_MASK            0x2
0363 #define BD71828_INT_VSYS_LOW_RES_MASK           0x4
0364 #define BD71828_INT_VSYS_LOW_DET_MASK           0x8
0365 #define BD71828_INT_VSYS_HALL_IN_MASK           0x10
0366 #define BD71828_INT_VSYS_HALL_TOGGLE_MASK       0x20
0367 #define BD71828_INT_VSYS_MON_RES_MASK           0x40
0368 #define BD71828_INT_VSYS_MON_DET_MASK           0x80
0369     /* Charger */
0370 #define BD71828_INT_CHG_DCIN_ILIM_MASK          0x1
0371 #define BD71828_INT_CHG_TOPOFF_TO_DONE_MASK     0x2
0372 #define BD71828_INT_CHG_WDG_TEMP_MASK           0x4
0373 #define BD71828_INT_CHG_WDG_TIME_MASK           0x8
0374 #define BD71828_INT_CHG_RECHARGE_RES_MASK       0x10
0375 #define BD71828_INT_CHG_RECHARGE_DET_MASK       0x20
0376 #define BD71828_INT_CHG_RANGED_TEMP_TRANSITION_MASK 0x40
0377 #define BD71828_INT_CHG_STATE_TRANSITION_MASK       0x80
0378     /* Battery */
0379 #define BD71828_INT_BAT_TEMP_NORMAL_MASK        0x1
0380 #define BD71828_INT_BAT_TEMP_ERANGE_MASK        0x2
0381 #define BD71828_INT_BAT_TEMP_WARN_MASK          0x4
0382 #define BD71828_INT_BAT_REMOVED_MASK            0x10
0383 #define BD71828_INT_BAT_DETECTED_MASK           0x20
0384 #define BD71828_INT_THERM_REMOVED_MASK          0x40
0385 #define BD71828_INT_THERM_DETECTED_MASK         0x80
0386     /* Battery Mon 1 */
0387 #define BD71828_INT_BAT_DEAD_MASK           0x2
0388 #define BD71828_INT_BAT_SHORTC_RES_MASK         0x4
0389 #define BD71828_INT_BAT_SHORTC_DET_MASK         0x8
0390 #define BD71828_INT_BAT_LOW_VOLT_RES_MASK       0x10
0391 #define BD71828_INT_BAT_LOW_VOLT_DET_MASK       0x20
0392 #define BD71828_INT_BAT_OVER_VOLT_RES_MASK      0x40
0393 #define BD71828_INT_BAT_OVER_VOLT_DET_MASK      0x80
0394     /* Battery Mon 2 */
0395 #define BD71828_INT_BAT_MON_RES_MASK            0x1
0396 #define BD71828_INT_BAT_MON_DET_MASK            0x2
0397     /* Battery Mon 3 (Coulomb counter) */
0398 #define BD71828_INT_BAT_CC_MON1_MASK            0x1
0399 #define BD71828_INT_BAT_CC_MON2_MASK            0x2
0400 #define BD71828_INT_BAT_CC_MON3_MASK            0x4
0401     /* Battery Mon 4 */
0402 #define BD71828_INT_BAT_OVER_CURR_1_RES_MASK        0x1
0403 #define BD71828_INT_BAT_OVER_CURR_1_DET_MASK        0x2
0404 #define BD71828_INT_BAT_OVER_CURR_2_RES_MASK        0x4
0405 #define BD71828_INT_BAT_OVER_CURR_2_DET_MASK        0x8
0406 #define BD71828_INT_BAT_OVER_CURR_3_RES_MASK        0x10
0407 #define BD71828_INT_BAT_OVER_CURR_3_DET_MASK        0x20
0408     /* Temperature */
0409 #define BD71828_INT_TEMP_BAT_LOW_RES_MASK       0x1
0410 #define BD71828_INT_TEMP_BAT_LOW_DET_MASK       0x2
0411 #define BD71828_INT_TEMP_BAT_HI_RES_MASK        0x4
0412 #define BD71828_INT_TEMP_BAT_HI_DET_MASK        0x8
0413 #define BD71828_INT_TEMP_CHIP_OVER_125_RES_MASK     0x10
0414 #define BD71828_INT_TEMP_CHIP_OVER_125_DET_MASK     0x20
0415 #define BD71828_INT_TEMP_CHIP_OVER_VF_RES_MASK      0x40
0416 #define BD71828_INT_TEMP_CHIP_OVER_VF_DET_MASK      0x80
0417     /* RTC Alarm */
0418 #define BD71828_INT_RTC0_MASK               0x1
0419 #define BD71828_INT_RTC1_MASK               0x2
0420 #define BD71828_INT_RTC2_MASK               0x4
0421
0422 #define BD71828_OUT_TYPE_MASK               0x2
0423 #define BD71828_OUT_TYPE_OPEN_DRAIN         0x0
0424 #define BD71828_OUT_TYPE_CMOS               0x2
0425
0426 #endif /* __LINUX_MFD_BD71828_H__ */