linux/mfd/rohm-bd71815.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Copyright 2021 ROHM Semiconductors.
0004  *
0005  * Author: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>
0006  *
0007  * Copyright 2014 Embest Technology Co. Ltd. Inc.
0008  *
0009  * Author: yanglsh@embest-tech.com
0010  */
0011
0012 #ifndef _MFD_BD71815_H
0013 #define _MFD_BD71815_H
0014
0015 #include <linux/regmap.h>
0016
0017 enum {
0018     BD71815_BUCK1   =   0,
0019     BD71815_BUCK2,
0020     BD71815_BUCK3,
0021     BD71815_BUCK4,
0022     BD71815_BUCK5,
0023     /* General Purpose */
0024     BD71815_LDO1,
0025     BD71815_LDO2,
0026     BD71815_LDO3,
0027     /* LDOs for SD Card and SD Card Interface */
0028     BD71815_LDO4,
0029     BD71815_LDO5,
0030     /* LDO for DDR Reference Voltage */
0031     BD71815_LDODVREF,
0032     /* LDO for Low-Power State Retention */
0033     BD71815_LDOLPSR,
0034     BD71815_WLED,
0035     BD71815_REGULATOR_CNT,
0036 };
0037
0038 #define BD71815_SUPPLY_STATE_ENABLED    0x1
0039
0040 enum {
0041     BD71815_REG_DEVICE      = 0,
0042     BD71815_REG_PWRCTRL,
0043     BD71815_REG_BUCK1_MODE,
0044     BD71815_REG_BUCK2_MODE,
0045     BD71815_REG_BUCK3_MODE,
0046     BD71815_REG_BUCK4_MODE,
0047     BD71815_REG_BUCK5_MODE,
0048     BD71815_REG_BUCK1_VOLT_H,
0049     BD71815_REG_BUCK1_VOLT_L,
0050     BD71815_REG_BUCK2_VOLT_H,
0051     BD71815_REG_BUCK2_VOLT_L,
0052     BD71815_REG_BUCK3_VOLT,
0053     BD71815_REG_BUCK4_VOLT,
0054     BD71815_REG_BUCK5_VOLT,
0055     BD71815_REG_LED_CTRL,
0056     BD71815_REG_LED_DIMM,
0057     BD71815_REG_LDO_MODE1,
0058     BD71815_REG_LDO_MODE2,
0059     BD71815_REG_LDO_MODE3,
0060     BD71815_REG_LDO_MODE4,
0061     BD71815_REG_LDO1_VOLT,
0062     BD71815_REG_LDO2_VOLT,
0063     BD71815_REG_LDO3_VOLT,
0064     BD71815_REG_LDO4_VOLT,
0065     BD71815_REG_LDO5_VOLT_H,
0066     BD71815_REG_LDO5_VOLT_L,
0067     BD71815_REG_BUCK_PD_DIS,
0068     BD71815_REG_LDO_PD_DIS,
0069     BD71815_REG_GPO,
0070     BD71815_REG_OUT32K,
0071     BD71815_REG_SEC,
0072     BD71815_REG_MIN,
0073     BD71815_REG_HOUR,
0074     BD71815_REG_WEEK,
0075     BD71815_REG_DAY,
0076     BD71815_REG_MONTH,
0077     BD71815_REG_YEAR,
0078     BD71815_REG_ALM0_SEC,
0079
0080     BD71815_REG_ALM1_SEC        = 0x2C,
0081
0082     BD71815_REG_ALM0_MASK       = 0x33,
0083     BD71815_REG_ALM1_MASK,
0084     BD71815_REG_ALM2,
0085     BD71815_REG_TRIM,
0086     BD71815_REG_CONF,
0087     BD71815_REG_SYS_INIT,
0088     BD71815_REG_CHG_STATE,
0089     BD71815_REG_CHG_LAST_STATE,
0090     BD71815_REG_BAT_STAT,
0091     BD71815_REG_DCIN_STAT,
0092     BD71815_REG_VSYS_STAT,
0093     BD71815_REG_CHG_STAT,
0094     BD71815_REG_CHG_WDT_STAT,
0095     BD71815_REG_BAT_TEMP,
0096     BD71815_REG_IGNORE_0,
0097     BD71815_REG_INHIBIT_0,
0098     BD71815_REG_DCIN_CLPS,
0099     BD71815_REG_VSYS_REG,
0100     BD71815_REG_VSYS_MAX,
0101     BD71815_REG_VSYS_MIN,
0102     BD71815_REG_CHG_SET1,
0103     BD71815_REG_CHG_SET2,
0104     BD71815_REG_CHG_WDT_PRE,
0105     BD71815_REG_CHG_WDT_FST,
0106     BD71815_REG_CHG_IPRE,
0107     BD71815_REG_CHG_IFST,
0108     BD71815_REG_CHG_IFST_TERM,
0109     BD71815_REG_CHG_VPRE,
0110     BD71815_REG_CHG_VBAT_1,
0111     BD71815_REG_CHG_VBAT_2,
0112     BD71815_REG_CHG_VBAT_3,
0113     BD71815_REG_CHG_LED_1,
0114     BD71815_REG_VF_TH,
0115     BD71815_REG_BAT_SET_1,
0116     BD71815_REG_BAT_SET_2,
0117     BD71815_REG_BAT_SET_3,
0118     BD71815_REG_ALM_VBAT_TH_U,
0119     BD71815_REG_ALM_VBAT_TH_L,
0120     BD71815_REG_ALM_DCIN_TH,
0121     BD71815_REG_ALM_VSYS_TH,
0122     BD71815_REG_VM_IBAT_U,
0123     BD71815_REG_VM_IBAT_L,
0124     BD71815_REG_VM_VBAT_U,
0125     BD71815_REG_VM_VBAT_L,
0126     BD71815_REG_VM_BTMP,
0127     BD71815_REG_VM_VTH,
0128     BD71815_REG_VM_DCIN_U,
0129     BD71815_REG_VM_DCIN_L,
0130     BD71815_REG_VM_VSYS,
0131     BD71815_REG_VM_VF,
0132     BD71815_REG_VM_OCI_PRE_U,
0133     BD71815_REG_VM_OCI_PRE_L,
0134     BD71815_REG_VM_OCV_PRE_U,
0135     BD71815_REG_VM_OCV_PRE_L,
0136     BD71815_REG_VM_OCI_PST_U,
0137     BD71815_REG_VM_OCI_PST_L,
0138     BD71815_REG_VM_OCV_PST_U,
0139     BD71815_REG_VM_OCV_PST_L,
0140     BD71815_REG_VM_SA_VBAT_U,
0141     BD71815_REG_VM_SA_VBAT_L,
0142     BD71815_REG_VM_SA_IBAT_U,
0143     BD71815_REG_VM_SA_IBAT_L,
0144     BD71815_REG_CC_CTRL,
0145     BD71815_REG_CC_BATCAP1_TH_U,
0146     BD71815_REG_CC_BATCAP1_TH_L,
0147     BD71815_REG_CC_BATCAP2_TH_U,
0148     BD71815_REG_CC_BATCAP2_TH_L,
0149     BD71815_REG_CC_BATCAP3_TH_U,
0150     BD71815_REG_CC_BATCAP3_TH_L,
0151     BD71815_REG_CC_STAT,
0152     BD71815_REG_CC_CCNTD_3,
0153     BD71815_REG_CC_CCNTD_2,
0154     BD71815_REG_CC_CCNTD_1,
0155     BD71815_REG_CC_CCNTD_0,
0156     BD71815_REG_CC_CURCD_U,
0157     BD71815_REG_CC_CURCD_L,
0158     BD71815_REG_VM_OCUR_THR_1,
0159     BD71815_REG_VM_OCUR_DUR_1,
0160     BD71815_REG_VM_OCUR_THR_2,
0161     BD71815_REG_VM_OCUR_DUR_2,
0162     BD71815_REG_VM_OCUR_THR_3,
0163     BD71815_REG_VM_OCUR_DUR_3,
0164     BD71815_REG_VM_OCUR_MON,
0165     BD71815_REG_VM_BTMP_OV_THR,
0166     BD71815_REG_VM_BTMP_OV_DUR,
0167     BD71815_REG_VM_BTMP_LO_THR,
0168     BD71815_REG_VM_BTMP_LO_DUR,
0169     BD71815_REG_VM_BTMP_MON,
0170     BD71815_REG_INT_EN_01,
0171
0172     BD71815_REG_INT_EN_11       = 0x95,
0173     BD71815_REG_INT_EN_12,
0174     BD71815_REG_INT_STAT,
0175     BD71815_REG_INT_STAT_01,
0176     BD71815_REG_INT_STAT_02,
0177     BD71815_REG_INT_STAT_03,
0178     BD71815_REG_INT_STAT_04,
0179     BD71815_REG_INT_STAT_05,
0180     BD71815_REG_INT_STAT_06,
0181     BD71815_REG_INT_STAT_07,
0182     BD71815_REG_INT_STAT_08,
0183     BD71815_REG_INT_STAT_09,
0184     BD71815_REG_INT_STAT_10,
0185     BD71815_REG_INT_STAT_11,
0186     BD71815_REG_INT_STAT_12,
0187     BD71815_REG_INT_UPDATE,
0188
0189     BD71815_REG_VM_VSYS_U       = 0xC0,
0190     BD71815_REG_VM_VSYS_L,
0191     BD71815_REG_VM_SA_VSYS_U,
0192     BD71815_REG_VM_SA_VSYS_L,
0193
0194     BD71815_REG_VM_SA_IBAT_MIN_U    = 0xD0,
0195     BD71815_REG_VM_SA_IBAT_MIN_L,
0196     BD71815_REG_VM_SA_IBAT_MAX_U,
0197     BD71815_REG_VM_SA_IBAT_MAX_L,
0198     BD71815_REG_VM_SA_VBAT_MIN_U,
0199     BD71815_REG_VM_SA_VBAT_MIN_L,
0200     BD71815_REG_VM_SA_VBAT_MAX_U,
0201     BD71815_REG_VM_SA_VBAT_MAX_L,
0202     BD71815_REG_VM_SA_VSYS_MIN_U,
0203     BD71815_REG_VM_SA_VSYS_MIN_L,
0204     BD71815_REG_VM_SA_VSYS_MAX_U,
0205     BD71815_REG_VM_SA_VSYS_MAX_L,
0206     BD71815_REG_VM_SA_MINMAX_CLR,
0207
0208     BD71815_REG_REX_CCNTD_3     = 0xE0,
0209     BD71815_REG_REX_CCNTD_2,
0210     BD71815_REG_REX_CCNTD_1,
0211     BD71815_REG_REX_CCNTD_0,
0212     BD71815_REG_REX_SA_VBAT_U,
0213     BD71815_REG_REX_SA_VBAT_L,
0214     BD71815_REG_REX_CTRL_1,
0215     BD71815_REG_REX_CTRL_2,
0216     BD71815_REG_FULL_CCNTD_3,
0217     BD71815_REG_FULL_CCNTD_2,
0218     BD71815_REG_FULL_CCNTD_1,
0219     BD71815_REG_FULL_CCNTD_0,
0220     BD71815_REG_FULL_CTRL,
0221
0222     BD71815_REG_CCNTD_CHG_3     = 0xF0,
0223     BD71815_REG_CCNTD_CHG_2,
0224
0225     BD71815_REG_TEST_MODE       = 0xFE,
0226     BD71815_MAX_REGISTER,
0227 };
0228
0229 /* BD71815_REG_BUCK1_MODE bits */
0230 #define BD71815_BUCK_RAMPRATE_MASK      0xC0
0231 #define BD71815_BUCK_RAMPRATE_10P00MV       0x0
0232 #define BD71815_BUCK_RAMPRATE_5P00MV        0x01
0233 #define BD71815_BUCK_RAMPRATE_2P50MV        0x02
0234 #define BD71815_BUCK_RAMPRATE_1P25MV        0x03
0235
0236 #define BD71815_BUCK_PWM_FIXED          BIT(4)
0237 #define BD71815_BUCK_SNVS_ON            BIT(3)
0238 #define BD71815_BUCK_RUN_ON         BIT(2)
0239 #define BD71815_BUCK_LPSR_ON            BIT(1)
0240 #define BD71815_BUCK_SUSP_ON            BIT(0)
0241
0242 /* BD71815_REG_BUCK1_VOLT_H bits */
0243 #define BD71815_BUCK_DVSSEL         BIT(7)
0244 #define BD71815_BUCK_STBY_DVS           BIT(6)
0245 #define BD71815_VOLT_MASK           0x3F
0246 #define BD71815_BUCK1_H_DEFAULT         0x14
0247 #define BD71815_BUCK1_L_DEFAULT         0x14
0248
0249 /* BD71815_REG_BUCK2_VOLT_H bits */
0250 #define BD71815_BUCK2_H_DEFAULT         0x14
0251 #define BD71815_BUCK2_L_DEFAULT         0x14
0252
0253 /* WLED output */
0254 /* current register mask */
0255 #define LED_DIMM_MASK               0x3f
0256 /* LED enable bits at LED_CTRL reg */
0257 #define LED_CHGDONE_EN              BIT(4)
0258 #define LED_RUN_ON              BIT(2)
0259 #define LED_LPSR_ON             BIT(1)
0260 #define LED_SUSP_ON             BIT(0)
0261
0262 /* BD71815_REG_LDO1_CTRL bits */
0263 #define LDO1_EN                 BIT(0)
0264 #define LDO2_EN                 BIT(1)
0265 #define LDO3_EN                 BIT(2)
0266 #define DVREF_EN                BIT(3)
0267 #define VOSNVS_SW_EN                BIT(4)
0268
0269 /* LDO_MODE1_register */
0270 #define LDO1_SNVS_ON                BIT(7)
0271 #define LDO1_RUN_ON             BIT(6)
0272 #define LDO1_LPSR_ON                BIT(5)
0273 #define LDO1_SUSP_ON                BIT(4)
0274 /* set => register control, unset => GPIO control */
0275 #define LDO4_MODE_MASK              BIT(3)
0276 #define LDO4_MODE_I2C               BIT(3)
0277 #define LDO4_MODE_GPIO              0
0278 /* set => register control, unset => start when DCIN connected */
0279 #define LDO3_MODE_MASK              BIT(2)
0280 #define LDO3_MODE_I2C               BIT(2)
0281 #define LDO3_MODE_DCIN              0
0282
0283 /* LDO_MODE2 register */
0284 #define LDO3_SNVS_ON                BIT(7)
0285 #define LDO3_RUN_ON             BIT(6)
0286 #define LDO3_LPSR_ON                BIT(5)
0287 #define LDO3_SUSP_ON                BIT(4)
0288 #define LDO2_SNVS_ON                BIT(3)
0289 #define LDO2_RUN_ON             BIT(2)
0290 #define LDO2_LPSR_ON                BIT(1)
0291 #define LDO2_SUSP_ON                BIT(0)
0292
0293
0294 /* LDO_MODE3 register */
0295 #define LDO5_SNVS_ON                BIT(7)
0296 #define LDO5_RUN_ON             BIT(6)
0297 #define LDO5_LPSR_ON                BIT(5)
0298 #define LDO5_SUSP_ON                BIT(4)
0299 #define LDO4_SNVS_ON                BIT(3)
0300 #define LDO4_RUN_ON             BIT(2)
0301 #define LDO4_LPSR_ON                BIT(1)
0302 #define LDO4_SUSP_ON                BIT(0)
0303
0304 /* LDO_MODE4 register */
0305 #define DVREF_SNVS_ON               BIT(7)
0306 #define DVREF_RUN_ON                BIT(6)
0307 #define DVREF_LPSR_ON               BIT(5)
0308 #define DVREF_SUSP_ON               BIT(4)
0309 #define LDO_LPSR_SNVS_ON            BIT(3)
0310 #define LDO_LPSR_RUN_ON             BIT(2)
0311 #define LDO_LPSR_LPSR_ON            BIT(1)
0312 #define LDO_LPSR_SUSP_ON            BIT(0)
0313
0314 /* BD71815_REG_OUT32K bits */
0315 #define OUT32K_EN               BIT(0)
0316 #define OUT32K_MODE             BIT(1)
0317 #define OUT32K_MODE_CMOS            BIT(1)
0318 #define OUT32K_MODE_OPEN_DRAIN          0
0319
0320 /* BD71815_REG_BAT_STAT bits */
0321 #define BAT_DET                 BIT(5)
0322 #define BAT_DET_OFFSET              5
0323 #define BAT_DET_DONE                BIT(4)
0324 #define VBAT_OV                 BIT(3)
0325 #define DBAT_DET                BIT(0)
0326
0327 /* BD71815_REG_VBUS_STAT bits */
0328 #define VBUS_DET                BIT(0)
0329
0330 #define BD71815_REG_RTC_START           BD71815_REG_SEC
0331 #define BD71815_REG_RTC_ALM_START       BD71815_REG_ALM0_SEC
0332
0333 /* BD71815_REG_ALM0_MASK bits */
0334 #define A0_ONESEC               BIT(7)
0335
0336 /* BD71815_REG_INT_EN_00 bits */
0337 #define ALMALE                  BIT(0)
0338
0339 /* BD71815_REG_INT_STAT_03 bits */
0340 #define DCIN_MON_DET                BIT(1)
0341 #define DCIN_MON_RES                BIT(0)
0342 #define POWERON_LONG                BIT(2)
0343 #define POWERON_MID             BIT(3)
0344 #define POWERON_SHORT               BIT(4)
0345 #define POWERON_PRESS               BIT(5)
0346
0347 /* BD71805_REG_INT_STAT_08 bits */
0348 #define VBAT_MON_DET                BIT(1)
0349 #define VBAT_MON_RES                BIT(0)
0350
0351 /* BD71805_REG_INT_STAT_11 bits */
0352 #define INT_STAT_11_VF_DET          BIT(7)
0353 #define INT_STAT_11_VF_RES          BIT(6)
0354 #define INT_STAT_11_VF125_DET           BIT(5)
0355 #define INT_STAT_11_VF125_RES           BIT(4)
0356 #define INT_STAT_11_OVTMP_DET           BIT(3)
0357 #define INT_STAT_11_OVTMP_RES           BIT(2)
0358 #define INT_STAT_11_LOTMP_DET           BIT(1)
0359 #define INT_STAT_11_LOTMP_RES           BIT(0)
0360
0361 #define VBAT_MON_DET                BIT(1)
0362 #define VBAT_MON_RES                BIT(0)
0363
0364 /* BD71815_REG_PWRCTRL bits */
0365 #define RESTARTEN               BIT(0)
0366
0367 /* BD71815_REG_GPO bits */
0368 #define READY_FORCE_LOW             BIT(2)
0369 #define BD71815_GPIO_DRIVE_MASK         BIT(4)
0370 #define BD71815_GPIO_OPEN_DRAIN         0
0371 #define BD71815_GPIO_CMOS           BIT(4)
0372
0373 /* BD71815 interrupt masks */
0374 enum {
0375     BD71815_INT_EN_01_BUCKAST_MASK  =   0x0F,
0376     BD71815_INT_EN_02_DCINAST_MASK  =   0x3E,
0377     BD71815_INT_EN_03_DCINAST_MASK  =   0x3F,
0378     BD71815_INT_EN_04_VSYSAST_MASK  =   0xCF,
0379     BD71815_INT_EN_05_CHGAST_MASK   =   0xFC,
0380     BD71815_INT_EN_06_BATAST_MASK   =   0xF3,
0381     BD71815_INT_EN_07_BMONAST_MASK  =   0xFE,
0382     BD71815_INT_EN_08_BMONAST_MASK  =   0x03,
0383     BD71815_INT_EN_09_BMONAST_MASK  =   0x07,
0384     BD71815_INT_EN_10_BMONAST_MASK  =   0x3F,
0385     BD71815_INT_EN_11_TMPAST_MASK   =   0xFF,
0386     BD71815_INT_EN_12_ALMAST_MASK   =   0x07,
0387 };
0388 /* BD71815 interrupt irqs */
0389 enum {
0390     /* BUCK reg interrupts */
0391     BD71815_INT_BUCK1_OCP,
0392     BD71815_INT_BUCK2_OCP,
0393     BD71815_INT_BUCK3_OCP,
0394     BD71815_INT_BUCK4_OCP,
0395     BD71815_INT_BUCK5_OCP,
0396     BD71815_INT_LED_OVP,
0397     BD71815_INT_LED_OCP,
0398     BD71815_INT_LED_SCP,
0399     /* DCIN1 interrupts */
0400     BD71815_INT_DCIN_RMV,
0401     BD71815_INT_CLPS_OUT,
0402     BD71815_INT_CLPS_IN,
0403     BD71815_INT_DCIN_OVP_RES,
0404     BD71815_INT_DCIN_OVP_DET,
0405     /* DCIN2 interrupts */
0406     BD71815_INT_DCIN_MON_RES,
0407     BD71815_INT_DCIN_MON_DET,
0408     BD71815_INT_WDOG,
0409     /* Vsys INT_STAT_04 */
0410     BD71815_INT_VSYS_UV_RES,
0411     BD71815_INT_VSYS_UV_DET,
0412     BD71815_INT_VSYS_LOW_RES,
0413     BD71815_INT_VSYS_LOW_DET,
0414     BD71815_INT_VSYS_MON_RES,
0415     BD71815_INT_VSYS_MON_DET,
0416     /* Charger INT_STAT_05 */
0417     BD71815_INT_CHG_WDG_TEMP,
0418     BD71815_INT_CHG_WDG_TIME,
0419     BD71815_INT_CHG_RECHARGE_RES,
0420     BD71815_INT_CHG_RECHARGE_DET,
0421     BD71815_INT_CHG_RANGED_TEMP_TRANSITION,
0422     BD71815_INT_CHG_STATE_TRANSITION,
0423     /* Battery  INT_STAT_06 */
0424     BD71815_INT_BAT_TEMP_NORMAL,
0425     BD71815_INT_BAT_TEMP_ERANGE,
0426     BD71815_INT_BAT_REMOVED,
0427     BD71815_INT_BAT_DETECTED,
0428     BD71815_INT_THERM_REMOVED,
0429     BD71815_INT_THERM_DETECTED,
0430     /* Battery Mon 1 INT_STAT_07 */
0431     BD71815_INT_BAT_DEAD,
0432     BD71815_INT_BAT_SHORTC_RES,
0433     BD71815_INT_BAT_SHORTC_DET,
0434     BD71815_INT_BAT_LOW_VOLT_RES,
0435     BD71815_INT_BAT_LOW_VOLT_DET,
0436     BD71815_INT_BAT_OVER_VOLT_RES,
0437     BD71815_INT_BAT_OVER_VOLT_DET,
0438     /* Battery Mon 2 INT_STAT_08 */
0439     BD71815_INT_BAT_MON_RES,
0440     BD71815_INT_BAT_MON_DET,
0441     /* Battery Mon 3 (Coulomb counter) INT_STAT_09 */
0442     BD71815_INT_BAT_CC_MON1,
0443     BD71815_INT_BAT_CC_MON2,
0444     BD71815_INT_BAT_CC_MON3,
0445     /* Battery Mon 4 INT_STAT_10 */
0446     BD71815_INT_BAT_OVER_CURR_1_RES,
0447     BD71815_INT_BAT_OVER_CURR_1_DET,
0448     BD71815_INT_BAT_OVER_CURR_2_RES,
0449     BD71815_INT_BAT_OVER_CURR_2_DET,
0450     BD71815_INT_BAT_OVER_CURR_3_RES,
0451     BD71815_INT_BAT_OVER_CURR_3_DET,
0452     /* Temperature INT_STAT_11 */
0453     BD71815_INT_TEMP_BAT_LOW_RES,
0454     BD71815_INT_TEMP_BAT_LOW_DET,
0455     BD71815_INT_TEMP_BAT_HI_RES,
0456     BD71815_INT_TEMP_BAT_HI_DET,
0457     BD71815_INT_TEMP_CHIP_OVER_125_RES,
0458     BD71815_INT_TEMP_CHIP_OVER_125_DET,
0459     BD71815_INT_TEMP_CHIP_OVER_VF_RES,
0460     BD71815_INT_TEMP_CHIP_OVER_VF_DET,
0461     /* RTC Alarm INT_STAT_12 */
0462     BD71815_INT_RTC0,
0463     BD71815_INT_RTC1,
0464     BD71815_INT_RTC2,
0465 };
0466
0467 #define BD71815_INT_BUCK1_OCP_MASK          BIT(0)
0468 #define BD71815_INT_BUCK2_OCP_MASK          BIT(1)
0469 #define BD71815_INT_BUCK3_OCP_MASK          BIT(2)
0470 #define BD71815_INT_BUCK4_OCP_MASK          BIT(3)
0471 #define BD71815_INT_BUCK5_OCP_MASK          BIT(4)
0472 #define BD71815_INT_LED_OVP_MASK            BIT(5)
0473 #define BD71815_INT_LED_OCP_MASK            BIT(6)
0474 #define BD71815_INT_LED_SCP_MASK            BIT(7)
0475
0476 #define BD71815_INT_DCIN_RMV_MASK           BIT(1)
0477 #define BD71815_INT_CLPS_OUT_MASK           BIT(2)
0478 #define BD71815_INT_CLPS_IN_MASK            BIT(3)
0479 #define BD71815_INT_DCIN_OVP_RES_MASK           BIT(4)
0480 #define BD71815_INT_DCIN_OVP_DET_MASK           BIT(5)
0481
0482 #define BD71815_INT_DCIN_MON_RES_MASK           BIT(0)
0483 #define BD71815_INT_DCIN_MON_DET_MASK           BIT(1)
0484 #define BD71815_INT_WDOG_MASK               BIT(6)
0485
0486 #define BD71815_INT_VSYS_UV_RES_MASK            BIT(0)
0487 #define BD71815_INT_VSYS_UV_DET_MASK            BIT(1)
0488 #define BD71815_INT_VSYS_LOW_RES_MASK           BIT(2)
0489 #define BD71815_INT_VSYS_LOW_DET_MASK           BIT(3)
0490 #define BD71815_INT_VSYS_MON_RES_MASK           BIT(6)
0491 #define BD71815_INT_VSYS_MON_DET_MASK           BIT(7)
0492
0493 #define BD71815_INT_CHG_WDG_TEMP_MASK           BIT(2)
0494 #define BD71815_INT_CHG_WDG_TIME_MASK           BIT(3)
0495 #define BD71815_INT_CHG_RECHARGE_RES_MASK       BIT(4)
0496 #define BD71815_INT_CHG_RECHARGE_DET_MASK       BIT(5)
0497 #define BD71815_INT_CHG_RANGED_TEMP_TRANSITION_MASK BIT(6)
0498 #define BD71815_INT_CHG_STATE_TRANSITION_MASK       BIT(7)
0499
0500 #define BD71815_INT_BAT_TEMP_NORMAL_MASK        BIT(0)
0501 #define BD71815_INT_BAT_TEMP_ERANGE_MASK        BIT(1)
0502 #define BD71815_INT_BAT_REMOVED_MASK            BIT(4)
0503 #define BD71815_INT_BAT_DETECTED_MASK           BIT(5)
0504 #define BD71815_INT_THERM_REMOVED_MASK          BIT(6)
0505 #define BD71815_INT_THERM_DETECTED_MASK         BIT(7)
0506
0507 #define BD71815_INT_BAT_DEAD_MASK           BIT(1)
0508 #define BD71815_INT_BAT_SHORTC_RES_MASK         BIT(2)
0509 #define BD71815_INT_BAT_SHORTC_DET_MASK         BIT(3)
0510 #define BD71815_INT_BAT_LOW_VOLT_RES_MASK       BIT(4)
0511 #define BD71815_INT_BAT_LOW_VOLT_DET_MASK       BIT(5)
0512 #define BD71815_INT_BAT_OVER_VOLT_RES_MASK      BIT(6)
0513 #define BD71815_INT_BAT_OVER_VOLT_DET_MASK      BIT(7)
0514
0515 #define BD71815_INT_BAT_MON_RES_MASK            BIT(0)
0516 #define BD71815_INT_BAT_MON_DET_MASK            BIT(1)
0517
0518 #define BD71815_INT_BAT_CC_MON1_MASK            BIT(0)
0519 #define BD71815_INT_BAT_CC_MON2_MASK            BIT(1)
0520 #define BD71815_INT_BAT_CC_MON3_MASK            BIT(2)
0521
0522 #define BD71815_INT_BAT_OVER_CURR_1_RES_MASK        BIT(0)
0523 #define BD71815_INT_BAT_OVER_CURR_1_DET_MASK        BIT(1)
0524 #define BD71815_INT_BAT_OVER_CURR_2_RES_MASK        BIT(2)
0525 #define BD71815_INT_BAT_OVER_CURR_2_DET_MASK        BIT(3)
0526 #define BD71815_INT_BAT_OVER_CURR_3_RES_MASK        BIT(4)
0527 #define BD71815_INT_BAT_OVER_CURR_3_DET_MASK        BIT(5)
0528
0529 #define BD71815_INT_TEMP_BAT_LOW_RES_MASK       BIT(0)
0530 #define BD71815_INT_TEMP_BAT_LOW_DET_MASK       BIT(1)
0531 #define BD71815_INT_TEMP_BAT_HI_RES_MASK        BIT(2)
0532 #define BD71815_INT_TEMP_BAT_HI_DET_MASK        BIT(3)
0533 #define BD71815_INT_TEMP_CHIP_OVER_125_RES_MASK     BIT(4)
0534 #define BD71815_INT_TEMP_CHIP_OVER_125_DET_MASK     BIT(5)
0535 #define BD71815_INT_TEMP_CHIP_OVER_VF_RES_MASK      BIT(6)
0536 #define BD71815_INT_TEMP_CHIP_OVER_VF_DET_MASK      BIT(7)
0537
0538 #define BD71815_INT_RTC0_MASK               BIT(0)
0539 #define BD71815_INT_RTC1_MASK               BIT(1)
0540 #define BD71815_INT_RTC2_MASK               BIT(2)
0541
0542 /* BD71815_REG_CC_CTRL bits */
0543 #define CCNTRST                     0x80
0544 #define CCNTENB                     0x40
0545 #define CCCALIB                     0x20
0546
0547 /* BD71815_REG_CC_CURCD */
0548 #define CURDIR_Discharging              0x8000
0549
0550 /* BD71815_REG_VM_SA_IBAT */
0551 #define IBAT_SA_DIR_Discharging             0x8000
0552
0553 /* BD71815_REG_REX_CTRL_1 bits */
0554 #define REX_CLR                     BIT(4)
0555
0556 /* BD71815_REG_REX_CTRL_1 bits */
0557 #define REX_PMU_STATE_MASK              BIT(2)
0558
0559 /* BD71815_REG_LED_CTRL bits */
0560 #define CHGDONE_LED_EN                  BIT(4)
0561
0562 #endif /* __LINUX_MFD_BD71815_H */