mfd/mt6359/core.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copyright (c) 2021 MediaTek Inc.
0004  */
0005
0006 #ifndef __MFD_MT6359_CORE_H__
0007 #define __MFD_MT6359_CORE_H__
0008
0009 enum mt6359_irq_top_status_shift {
0010     MT6359_BUCK_TOP = 0,
0011     MT6359_LDO_TOP,
0012     MT6359_PSC_TOP,
0013     MT6359_SCK_TOP,
0014     MT6359_BM_TOP,
0015     MT6359_HK_TOP,
0016     MT6359_AUD_TOP = 7,
0017     MT6359_MISC_TOP,
0018 };
0019
0020 enum mt6359_irq_numbers {
0021     MT6359_IRQ_VCORE_OC = 1,
0022     MT6359_IRQ_VGPU11_OC,
0023     MT6359_IRQ_VGPU12_OC,
0024     MT6359_IRQ_VMODEM_OC,
0025     MT6359_IRQ_VPROC1_OC,
0026     MT6359_IRQ_VPROC2_OC,
0027     MT6359_IRQ_VS1_OC,
0028     MT6359_IRQ_VS2_OC,
0029     MT6359_IRQ_VPA_OC = 9,
0030     MT6359_IRQ_VFE28_OC = 16,
0031     MT6359_IRQ_VXO22_OC,
0032     MT6359_IRQ_VRF18_OC,
0033     MT6359_IRQ_VRF12_OC,
0034     MT6359_IRQ_VEFUSE_OC,
0035     MT6359_IRQ_VCN33_1_OC,
0036     MT6359_IRQ_VCN33_2_OC,
0037     MT6359_IRQ_VCN13_OC,
0038     MT6359_IRQ_VCN18_OC,
0039     MT6359_IRQ_VA09_OC,
0040     MT6359_IRQ_VCAMIO_OC,
0041     MT6359_IRQ_VA12_OC,
0042     MT6359_IRQ_VAUX18_OC,
0043     MT6359_IRQ_VAUD18_OC,
0044     MT6359_IRQ_VIO18_OC,
0045     MT6359_IRQ_VSRAM_PROC1_OC,
0046     MT6359_IRQ_VSRAM_PROC2_OC,
0047     MT6359_IRQ_VSRAM_OTHERS_OC,
0048     MT6359_IRQ_VSRAM_MD_OC,
0049     MT6359_IRQ_VEMC_OC,
0050     MT6359_IRQ_VSIM1_OC,
0051     MT6359_IRQ_VSIM2_OC,
0052     MT6359_IRQ_VUSB_OC,
0053     MT6359_IRQ_VRFCK_OC,
0054     MT6359_IRQ_VBBCK_OC,
0055     MT6359_IRQ_VBIF28_OC,
0056     MT6359_IRQ_VIBR_OC,
0057     MT6359_IRQ_VIO28_OC,
0058     MT6359_IRQ_VM18_OC,
0059     MT6359_IRQ_VUFS_OC = 45,
0060     MT6359_IRQ_PWRKEY = 48,
0061     MT6359_IRQ_HOMEKEY,
0062     MT6359_IRQ_PWRKEY_R,
0063     MT6359_IRQ_HOMEKEY_R,
0064     MT6359_IRQ_NI_LBAT_INT,
0065     MT6359_IRQ_CHRDET_EDGE = 53,
0066     MT6359_IRQ_RTC = 64,
0067     MT6359_IRQ_FG_BAT_H = 80,
0068     MT6359_IRQ_FG_BAT_L,
0069     MT6359_IRQ_FG_CUR_H,
0070     MT6359_IRQ_FG_CUR_L,
0071     MT6359_IRQ_FG_ZCV = 84,
0072     MT6359_IRQ_FG_N_CHARGE_L = 87,
0073     MT6359_IRQ_FG_IAVG_H,
0074     MT6359_IRQ_FG_IAVG_L = 89,
0075     MT6359_IRQ_FG_DISCHARGE = 91,
0076     MT6359_IRQ_FG_CHARGE,
0077     MT6359_IRQ_BATON_LV = 96,
0078     MT6359_IRQ_BATON_BAT_IN = 98,
0079     MT6359_IRQ_BATON_BAT_OU,
0080     MT6359_IRQ_BIF = 100,
0081     MT6359_IRQ_BAT_H = 112,
0082     MT6359_IRQ_BAT_L,
0083     MT6359_IRQ_BAT2_H,
0084     MT6359_IRQ_BAT2_L,
0085     MT6359_IRQ_BAT_TEMP_H,
0086     MT6359_IRQ_BAT_TEMP_L,
0087     MT6359_IRQ_THR_H,
0088     MT6359_IRQ_THR_L,
0089     MT6359_IRQ_AUXADC_IMP,
0090     MT6359_IRQ_NAG_C_DLTV = 121,
0091     MT6359_IRQ_AUDIO = 128,
0092     MT6359_IRQ_ACCDET = 133,
0093     MT6359_IRQ_ACCDET_EINT0,
0094     MT6359_IRQ_ACCDET_EINT1,
0095     MT6359_IRQ_SPI_CMD_ALERT = 144,
0096     MT6359_IRQ_NR,
0097 };
0098
0099 #define MT6359_IRQ_BUCK_BASE MT6359_IRQ_VCORE_OC
0100 #define MT6359_IRQ_LDO_BASE MT6359_IRQ_VFE28_OC
0101 #define MT6359_IRQ_PSC_BASE MT6359_IRQ_PWRKEY
0102 #define MT6359_IRQ_SCK_BASE MT6359_IRQ_RTC
0103 #define MT6359_IRQ_BM_BASE MT6359_IRQ_FG_BAT_H
0104 #define MT6359_IRQ_HK_BASE MT6359_IRQ_BAT_H
0105 #define MT6359_IRQ_AUD_BASE MT6359_IRQ_AUDIO
0106 #define MT6359_IRQ_MISC_BASE MT6359_IRQ_SPI_CMD_ALERT
0107
0108 #define MT6359_IRQ_BUCK_BITS (MT6359_IRQ_VPA_OC - MT6359_IRQ_BUCK_BASE + 1)
0109 #define MT6359_IRQ_LDO_BITS (MT6359_IRQ_VUFS_OC - MT6359_IRQ_LDO_BASE + 1)
0110 #define MT6359_IRQ_PSC_BITS \
0111     (MT6359_IRQ_CHRDET_EDGE - MT6359_IRQ_PSC_BASE + 1)
0112 #define MT6359_IRQ_SCK_BITS (MT6359_IRQ_RTC - MT6359_IRQ_SCK_BASE + 1)
0113 #define MT6359_IRQ_BM_BITS (MT6359_IRQ_BIF - MT6359_IRQ_BM_BASE + 1)
0114 #define MT6359_IRQ_HK_BITS (MT6359_IRQ_NAG_C_DLTV - MT6359_IRQ_HK_BASE + 1)
0115 #define MT6359_IRQ_AUD_BITS \
0116     (MT6359_IRQ_ACCDET_EINT1 - MT6359_IRQ_AUD_BASE + 1)
0117 #define MT6359_IRQ_MISC_BITS    \
0118     (MT6359_IRQ_SPI_CMD_ALERT - MT6359_IRQ_MISC_BASE + 1)
0119
0120 #define MT6359_TOP_GEN(sp)  \
0121 {   \
0122     .hwirq_base = MT6359_IRQ_##sp##_BASE,   \
0123     .num_int_regs = \
0124         ((MT6359_IRQ_##sp##_BITS - 1) / \
0125         MTK_PMIC_REG_WIDTH) + 1,    \
0126     .en_reg = MT6359_##sp##_TOP_INT_CON0,   \
0127     .en_reg_shift = 0x6,    \
0128     .sta_reg = MT6359_##sp##_TOP_INT_STATUS0,   \
0129     .sta_reg_shift = 0x2,   \
0130     .top_offset = MT6359_##sp##_TOP,    \
0131 }
0132
0133 #endif /* __MFD_MT6359_CORE_H__ */