mfd/mt6358/core.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copyright (c) 2020 MediaTek Inc.
0004  */
0005
0006 #ifndef __MFD_MT6358_CORE_H__
0007 #define __MFD_MT6358_CORE_H__
0008
0009 struct irq_top_t {
0010     int hwirq_base;
0011     unsigned int num_int_regs;
0012     unsigned int en_reg;
0013     unsigned int en_reg_shift;
0014     unsigned int sta_reg;
0015     unsigned int sta_reg_shift;
0016     unsigned int top_offset;
0017 };
0018
0019 struct pmic_irq_data {
0020     unsigned int num_top;
0021     unsigned int num_pmic_irqs;
0022     unsigned short top_int_status_reg;
0023     bool *enable_hwirq;
0024     bool *cache_hwirq;
0025     const struct irq_top_t *pmic_ints;
0026 };
0027
0028 enum mt6358_irq_top_status_shift {
0029     MT6358_BUCK_TOP = 0,
0030     MT6358_LDO_TOP,
0031     MT6358_PSC_TOP,
0032     MT6358_SCK_TOP,
0033     MT6358_BM_TOP,
0034     MT6358_HK_TOP,
0035     MT6358_AUD_TOP,
0036     MT6358_MISC_TOP,
0037 };
0038
0039 enum mt6358_irq_numbers {
0040     MT6358_IRQ_VPROC11_OC = 0,
0041     MT6358_IRQ_VPROC12_OC,
0042     MT6358_IRQ_VCORE_OC,
0043     MT6358_IRQ_VGPU_OC,
0044     MT6358_IRQ_VMODEM_OC,
0045     MT6358_IRQ_VDRAM1_OC,
0046     MT6358_IRQ_VS1_OC,
0047     MT6358_IRQ_VS2_OC,
0048     MT6358_IRQ_VPA_OC,
0049     MT6358_IRQ_VCORE_PREOC,
0050     MT6358_IRQ_VFE28_OC = 16,
0051     MT6358_IRQ_VXO22_OC,
0052     MT6358_IRQ_VRF18_OC,
0053     MT6358_IRQ_VRF12_OC,
0054     MT6358_IRQ_VEFUSE_OC,
0055     MT6358_IRQ_VCN33_OC,
0056     MT6358_IRQ_VCN28_OC,
0057     MT6358_IRQ_VCN18_OC,
0058     MT6358_IRQ_VCAMA1_OC,
0059     MT6358_IRQ_VCAMA2_OC,
0060     MT6358_IRQ_VCAMD_OC,
0061     MT6358_IRQ_VCAMIO_OC,
0062     MT6358_IRQ_VLDO28_OC,
0063     MT6358_IRQ_VA12_OC,
0064     MT6358_IRQ_VAUX18_OC,
0065     MT6358_IRQ_VAUD28_OC,
0066     MT6358_IRQ_VIO28_OC,
0067     MT6358_IRQ_VIO18_OC,
0068     MT6358_IRQ_VSRAM_PROC11_OC,
0069     MT6358_IRQ_VSRAM_PROC12_OC,
0070     MT6358_IRQ_VSRAM_OTHERS_OC,
0071     MT6358_IRQ_VSRAM_GPU_OC,
0072     MT6358_IRQ_VDRAM2_OC,
0073     MT6358_IRQ_VMC_OC,
0074     MT6358_IRQ_VMCH_OC,
0075     MT6358_IRQ_VEMC_OC,
0076     MT6358_IRQ_VSIM1_OC,
0077     MT6358_IRQ_VSIM2_OC,
0078     MT6358_IRQ_VIBR_OC,
0079     MT6358_IRQ_VUSB_OC,
0080     MT6358_IRQ_VBIF28_OC,
0081     MT6358_IRQ_PWRKEY = 48,
0082     MT6358_IRQ_HOMEKEY,
0083     MT6358_IRQ_PWRKEY_R,
0084     MT6358_IRQ_HOMEKEY_R,
0085     MT6358_IRQ_NI_LBAT_INT,
0086     MT6358_IRQ_CHRDET,
0087     MT6358_IRQ_CHRDET_EDGE,
0088     MT6358_IRQ_VCDT_HV_DET,
0089     MT6358_IRQ_RTC = 64,
0090     MT6358_IRQ_FG_BAT0_H = 80,
0091     MT6358_IRQ_FG_BAT0_L,
0092     MT6358_IRQ_FG_CUR_H,
0093     MT6358_IRQ_FG_CUR_L,
0094     MT6358_IRQ_FG_ZCV,
0095     MT6358_IRQ_FG_BAT1_H,
0096     MT6358_IRQ_FG_BAT1_L,
0097     MT6358_IRQ_FG_N_CHARGE_L,
0098     MT6358_IRQ_FG_IAVG_H,
0099     MT6358_IRQ_FG_IAVG_L,
0100     MT6358_IRQ_FG_TIME_H,
0101     MT6358_IRQ_FG_DISCHARGE,
0102     MT6358_IRQ_FG_CHARGE,
0103     MT6358_IRQ_BATON_LV = 96,
0104     MT6358_IRQ_BATON_HT,
0105     MT6358_IRQ_BATON_BAT_IN,
0106     MT6358_IRQ_BATON_BAT_OUT,
0107     MT6358_IRQ_BIF,
0108     MT6358_IRQ_BAT_H = 112,
0109     MT6358_IRQ_BAT_L,
0110     MT6358_IRQ_BAT2_H,
0111     MT6358_IRQ_BAT2_L,
0112     MT6358_IRQ_BAT_TEMP_H,
0113     MT6358_IRQ_BAT_TEMP_L,
0114     MT6358_IRQ_AUXADC_IMP,
0115     MT6358_IRQ_NAG_C_DLTV,
0116     MT6358_IRQ_AUDIO = 128,
0117     MT6358_IRQ_ACCDET = 133,
0118     MT6358_IRQ_ACCDET_EINT0,
0119     MT6358_IRQ_ACCDET_EINT1,
0120     MT6358_IRQ_SPI_CMD_ALERT = 144,
0121     MT6358_IRQ_NR,
0122 };
0123
0124 #define MT6358_IRQ_BUCK_BASE MT6358_IRQ_VPROC11_OC
0125 #define MT6358_IRQ_LDO_BASE MT6358_IRQ_VFE28_OC
0126 #define MT6358_IRQ_PSC_BASE MT6358_IRQ_PWRKEY
0127 #define MT6358_IRQ_SCK_BASE MT6358_IRQ_RTC
0128 #define MT6358_IRQ_BM_BASE MT6358_IRQ_FG_BAT0_H
0129 #define MT6358_IRQ_HK_BASE MT6358_IRQ_BAT_H
0130 #define MT6358_IRQ_AUD_BASE MT6358_IRQ_AUDIO
0131 #define MT6358_IRQ_MISC_BASE MT6358_IRQ_SPI_CMD_ALERT
0132
0133 #define MT6358_IRQ_BUCK_BITS (MT6358_IRQ_VCORE_PREOC - MT6358_IRQ_BUCK_BASE + 1)
0134 #define MT6358_IRQ_LDO_BITS (MT6358_IRQ_VBIF28_OC - MT6358_IRQ_LDO_BASE + 1)
0135 #define MT6358_IRQ_PSC_BITS (MT6358_IRQ_VCDT_HV_DET - MT6358_IRQ_PSC_BASE + 1)
0136 #define MT6358_IRQ_SCK_BITS (MT6358_IRQ_RTC - MT6358_IRQ_SCK_BASE + 1)
0137 #define MT6358_IRQ_BM_BITS (MT6358_IRQ_BIF - MT6358_IRQ_BM_BASE + 1)
0138 #define MT6358_IRQ_HK_BITS (MT6358_IRQ_NAG_C_DLTV - MT6358_IRQ_HK_BASE + 1)
0139 #define MT6358_IRQ_AUD_BITS (MT6358_IRQ_ACCDET_EINT1 - MT6358_IRQ_AUD_BASE + 1)
0140 #define MT6358_IRQ_MISC_BITS    \
0141     (MT6358_IRQ_SPI_CMD_ALERT - MT6358_IRQ_MISC_BASE + 1)
0142
0143 #define MT6358_TOP_GEN(sp)  \
0144 {   \
0145     .hwirq_base = MT6358_IRQ_##sp##_BASE,   \
0146     .num_int_regs = \
0147         ((MT6358_IRQ_##sp##_BITS - 1) / \
0148         MTK_PMIC_REG_WIDTH) + 1,    \
0149     .en_reg = MT6358_##sp##_TOP_INT_CON0,   \
0150     .en_reg_shift = 0x6,    \
0151     .sta_reg = MT6358_##sp##_TOP_INT_STATUS0,   \
0152     .sta_reg_shift = 0x2,   \
0153     .top_offset = MT6358_##sp##_TOP,    \
0154 }
0155
0156 #endif /* __MFD_MT6358_CORE_H__ */