mfd/mt6357/core.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (c) 2022 BayLibre, SAS
0004  * Author: Fabien Parent <fparent@baylibre.com>
0005  */
0006
0007 #ifndef __MFD_MT6357_CORE_H__
0008 #define __MFD_MT6357_CORE_H__
0009
0010 enum mt6357_irq_top_status_shift {
0011     MT6357_BUCK_TOP = 0,
0012     MT6357_LDO_TOP,
0013     MT6357_PSC_TOP,
0014     MT6357_SCK_TOP,
0015     MT6357_BM_TOP,
0016     MT6357_HK_TOP,
0017     MT6357_XPP_TOP,
0018     MT6357_AUD_TOP,
0019     MT6357_MISC_TOP,
0020 };
0021
0022 enum mt6357_irq_numbers {
0023     MT6357_IRQ_VPROC_OC = 0,
0024     MT6357_IRQ_VCORE_OC,
0025     MT6357_IRQ_VMODEM_OC,
0026     MT6357_IRQ_VS1_OC,
0027     MT6357_IRQ_VPA_OC,
0028     MT6357_IRQ_VCORE_PREOC,
0029     MT6357_IRQ_VFE28_OC = 16,
0030     MT6357_IRQ_VXO22_OC,
0031     MT6357_IRQ_VRF18_OC,
0032     MT6357_IRQ_VRF12_OC,
0033     MT6357_IRQ_VEFUSE_OC,
0034     MT6357_IRQ_VCN33_OC,
0035     MT6357_IRQ_VCN28_OC,
0036     MT6357_IRQ_VCN18_OC,
0037     MT6357_IRQ_VCAMA_OC,
0038     MT6357_IRQ_VCAMD_OC,
0039     MT6357_IRQ_VCAMIO_OC,
0040     MT6357_IRQ_VLDO28_OC,
0041     MT6357_IRQ_VUSB33_OC,
0042     MT6357_IRQ_VAUX18_OC,
0043     MT6357_IRQ_VAUD28_OC,
0044     MT6357_IRQ_VIO28_OC,
0045     MT6357_IRQ_VIO18_OC,
0046     MT6357_IRQ_VSRAM_PROC_OC,
0047     MT6357_IRQ_VSRAM_OTHERS_OC,
0048     MT6357_IRQ_VIBR_OC,
0049     MT6357_IRQ_VDRAM_OC,
0050     MT6357_IRQ_VMC_OC,
0051     MT6357_IRQ_VMCH_OC,
0052     MT6357_IRQ_VEMC_OC,
0053     MT6357_IRQ_VSIM1_OC,
0054     MT6357_IRQ_VSIM2_OC,
0055     MT6357_IRQ_PWRKEY = 48,
0056     MT6357_IRQ_HOMEKEY,
0057     MT6357_IRQ_PWRKEY_R,
0058     MT6357_IRQ_HOMEKEY_R,
0059     MT6357_IRQ_NI_LBAT_INT,
0060     MT6357_IRQ_CHRDET,
0061     MT6357_IRQ_CHRDET_EDGE,
0062     MT6357_IRQ_VCDT_HV_DET,
0063     MT6357_IRQ_WATCHDOG,
0064     MT6357_IRQ_VBATON_UNDET,
0065     MT6357_IRQ_BVALID_DET,
0066     MT6357_IRQ_OV,
0067     MT6357_IRQ_RTC = 64,
0068     MT6357_IRQ_FG_BAT0_H = 80,
0069     MT6357_IRQ_FG_BAT0_L,
0070     MT6357_IRQ_FG_CUR_H,
0071     MT6357_IRQ_FG_CUR_L,
0072     MT6357_IRQ_FG_ZCV,
0073     MT6357_IRQ_BATON_LV = 96,
0074     MT6357_IRQ_BATON_HT,
0075     MT6357_IRQ_BAT_H = 112,
0076     MT6357_IRQ_BAT_L,
0077     MT6357_IRQ_AUXADC_IMP,
0078     MT6357_IRQ_NAG_C_DLTV,
0079     MT6357_IRQ_AUDIO = 128,
0080     MT6357_IRQ_ACCDET = 133,
0081     MT6357_IRQ_ACCDET_EINT0,
0082     MT6357_IRQ_ACCDET_EINT1,
0083     MT6357_IRQ_SPI_CMD_ALERT = 144,
0084     MT6357_IRQ_NR,
0085 };
0086
0087 #define MT6357_IRQ_BUCK_BASE    MT6357_IRQ_VPROC_OC
0088 #define MT6357_IRQ_LDO_BASE MT6357_IRQ_VFE28_OC
0089 #define MT6357_IRQ_PSC_BASE MT6357_IRQ_PWRKEY
0090 #define MT6357_IRQ_SCK_BASE MT6357_IRQ_RTC
0091 #define MT6357_IRQ_BM_BASE  MT6357_IRQ_FG_BAT0_H
0092 #define MT6357_IRQ_HK_BASE  MT6357_IRQ_BAT_H
0093 #define MT6357_IRQ_AUD_BASE MT6357_IRQ_AUDIO
0094 #define MT6357_IRQ_MISC_BASE    MT6357_IRQ_SPI_CMD_ALERT
0095
0096 #define MT6357_IRQ_BUCK_BITS (MT6357_IRQ_VCORE_PREOC - MT6357_IRQ_BUCK_BASE + 1)
0097 #define MT6357_IRQ_LDO_BITS (MT6357_IRQ_VSIM2_OC - MT6357_IRQ_LDO_BASE + 1)
0098 #define MT6357_IRQ_PSC_BITS (MT6357_IRQ_VCDT_HV_DET - MT6357_IRQ_PSC_BASE + 1)
0099 #define MT6357_IRQ_SCK_BITS (MT6357_IRQ_RTC - MT6357_IRQ_SCK_BASE + 1)
0100 #define MT6357_IRQ_BM_BITS (MT6357_IRQ_BATON_HT - MT6357_IRQ_BM_BASE + 1)
0101 #define MT6357_IRQ_HK_BITS (MT6357_IRQ_NAG_C_DLTV - MT6357_IRQ_HK_BASE + 1)
0102 #define MT6357_IRQ_AUD_BITS (MT6357_IRQ_ACCDET_EINT1 - MT6357_IRQ_AUD_BASE + 1)
0103 #define MT6357_IRQ_MISC_BITS    \
0104     (MT6357_IRQ_SPI_CMD_ALERT - MT6357_IRQ_MISC_BASE + 1)
0105
0106 #define MT6357_TOP_GEN(sp)  \
0107 {   \
0108     .hwirq_base = MT6357_IRQ_##sp##_BASE,   \
0109     .num_int_regs = \
0110         ((MT6357_IRQ_##sp##_BITS - 1) / \
0111         MTK_PMIC_REG_WIDTH) + 1,    \
0112     .en_reg = MT6357_##sp##_TOP_INT_CON0,   \
0113     .en_reg_shift = 0x6,    \
0114     .sta_reg = MT6357_##sp##_TOP_INT_STATUS0,   \
0115     .sta_reg_shift = 0x2,   \
0116     .top_offset = MT6357_##sp##_TOP,    \
0117 }
0118
0119 #endif /* __MFD_MT6357_CORE_H__ */