mfd/mt6332/core.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (c) 2022 AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
0004  */
0005
0006 #ifndef __MFD_MT6332_CORE_H__
0007 #define __MFD_MT6332_CORE_H__
0008
0009 enum mt6332_irq_status_numbers {
0010     MT6332_IRQ_STATUS_CHR_COMPLETE = 0,
0011     MT6332_IRQ_STATUS_THERMAL_SD,
0012     MT6332_IRQ_STATUS_THERMAL_REG_IN,
0013     MT6332_IRQ_STATUS_THERMAL_REG_OUT,
0014     MT6332_IRQ_STATUS_OTG_OC,
0015     MT6332_IRQ_STATUS_CHR_OC,
0016     MT6332_IRQ_STATUS_OTG_THERMAL,
0017     MT6332_IRQ_STATUS_CHRIN_SHORT,
0018     MT6332_IRQ_STATUS_DRVCDT_SHORT,
0019     MT6332_IRQ_STATUS_PLUG_IN_FLASH,
0020     MT6332_IRQ_STATUS_CHRWDT_FLAG,
0021     MT6332_IRQ_STATUS_FLASH_EN_TIMEOUT,
0022     MT6332_IRQ_STATUS_FLASH_VLED1_SHORT,
0023     MT6332_IRQ_STATUS_FLASH_VLED1_OPEN = 13,
0024     MT6332_IRQ_STATUS_OV = 16,
0025     MT6332_IRQ_STATUS_BVALID_DET,
0026     MT6332_IRQ_STATUS_VBATON_UNDET,
0027     MT6332_IRQ_STATUS_CHR_PLUG_IN,
0028     MT6332_IRQ_STATUS_CHR_PLUG_OUT,
0029     MT6332_IRQ_STATUS_BC11_TIMEOUT,
0030     MT6332_IRQ_STATUS_FLASH_VLED2_SHORT,
0031     MT6332_IRQ_STATUS_FLASH_VLED2_OPEN = 23,
0032     MT6332_IRQ_STATUS_THR_H = 32,
0033     MT6332_IRQ_STATUS_THR_L,
0034     MT6332_IRQ_STATUS_BAT_H,
0035     MT6332_IRQ_STATUS_BAT_L,
0036     MT6332_IRQ_STATUS_M3_H,
0037     MT6332_IRQ_STATUS_M3_L,
0038     MT6332_IRQ_STATUS_FG_BAT_H,
0039     MT6332_IRQ_STATUS_FG_BAT_L,
0040     MT6332_IRQ_STATUS_FG_CUR_H,
0041     MT6332_IRQ_STATUS_FG_CUR_L,
0042     MT6332_IRQ_STATUS_SPKL_D,
0043     MT6332_IRQ_STATUS_SPKL_AB,
0044     MT6332_IRQ_STATUS_BIF,
0045     MT6332_IRQ_STATUS_VWLED_OC = 45,
0046     MT6332_IRQ_STATUS_VDRAM_OC = 48,
0047     MT6332_IRQ_STATUS_VDVFS2_OC,
0048     MT6332_IRQ_STATUS_VRF1_OC,
0049     MT6332_IRQ_STATUS_VRF2_OC,
0050     MT6332_IRQ_STATUS_VPA_OC,
0051     MT6332_IRQ_STATUS_VSBST_OC,
0052     MT6332_IRQ_STATUS_LDO_OC,
0053     MT6332_IRQ_STATUS_NR,
0054 };
0055
0056 #define MT6332_IRQ_CON0_BASE    MT6332_IRQ_STATUS_CHR_COMPLETE
0057 #define MT6332_IRQ_CON0_BITS    (MT6332_IRQ_STATUS_FLASH_VLED1_OPEN + 1)
0058 #define MT6332_IRQ_CON1_BASE    MT6332_IRQ_STATUS_OV
0059 #define MT6332_IRQ_CON1_BITS    (MT6332_IRQ_STATUS_FLASH_VLED2_OPEN - MT6332_IRQ_STATUS_OV + 1)
0060 #define MT6332_IRQ_CON2_BASE    MT6332_IRQ_STATUS_THR_H
0061 #define MT6332_IRQ_CON2_BITS    (MT6332_IRQ_STATUS_VWLED_OC - MT6332_IRQ_STATUS_THR_H + 1)
0062 #define MT6332_IRQ_CON3_BASE    MT6332_IRQ_STATUS_VDRAM_OC
0063 #define MT6332_IRQ_CON3_BITS    (MT6332_IRQ_STATUS_LDO_OC - MT6332_IRQ_STATUS_VDRAM_OC + 1)
0064
0065 #endif /* __MFD_MT6332_CORE_H__ */