mfd/mt6331/core.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (c) 2022 AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
0004  */
0005
0006 #ifndef __MFD_MT6331_CORE_H__
0007 #define __MFD_MT6331_CORE_H__
0008
0009 enum mt6331_irq_status_numbers {
0010     MT6331_IRQ_STATUS_PWRKEY = 0,
0011     MT6331_IRQ_STATUS_HOMEKEY,
0012     MT6331_IRQ_STATUS_CHRDET,
0013     MT6331_IRQ_STATUS_THR_H,
0014     MT6331_IRQ_STATUS_THR_L,
0015     MT6331_IRQ_STATUS_BAT_H,
0016     MT6331_IRQ_STATUS_BAT_L,
0017     MT6331_IRQ_STATUS_RTC,
0018     MT6331_IRQ_STATUS_AUDIO,
0019     MT6331_IRQ_STATUS_MAD,
0020     MT6331_IRQ_STATUS_ACCDET,
0021     MT6331_IRQ_STATUS_ACCDET_EINT,
0022     MT6331_IRQ_STATUS_ACCDET_NEGV = 12,
0023     MT6331_IRQ_STATUS_VDVFS11_OC = 16,
0024     MT6331_IRQ_STATUS_VDVFS12_OC,
0025     MT6331_IRQ_STATUS_VDVFS13_OC,
0026     MT6331_IRQ_STATUS_VDVFS14_OC,
0027     MT6331_IRQ_STATUS_GPU_OC,
0028     MT6331_IRQ_STATUS_VCORE1_OC,
0029     MT6331_IRQ_STATUS_VCORE2_OC,
0030     MT6331_IRQ_STATUS_VIO18_OC,
0031     MT6331_IRQ_STATUS_LDO_OC,
0032     MT6331_IRQ_STATUS_NR,
0033 };
0034
0035 #define MT6331_IRQ_CON0_BASE    MT6331_IRQ_STATUS_PWRKEY
0036 #define MT6331_IRQ_CON0_BITS    (MT6331_IRQ_STATUS_ACCDET_NEGV + 1)
0037 #define MT6331_IRQ_CON1_BASE    MT6331_IRQ_STATUS_VDVFS11_OC
0038 #define MT6331_IRQ_CON1_BITS    (MT6331_IRQ_STATUS_LDO_OC - MT6331_IRQ_STATUS_VDFS11_OC + 1)
0039
0040 #endif /* __MFD_MT6331_CORE_H__ */