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0001 /* SPDX-License-Identifier: GPL-2.0+ */
0002 /*
0003  * max8997-private.h - Voltage regulator driver for the Maxim 8997
0004  *
0005  *  Copyright (C) 2010 Samsung Electrnoics
0006  *  MyungJoo Ham <myungjoo.ham@samsung.com>
0007  */
0008 
0009 #ifndef __LINUX_MFD_MAX8997_PRIV_H
0010 #define __LINUX_MFD_MAX8997_PRIV_H
0011 
0012 #include <linux/i2c.h>
0013 #include <linux/export.h>
0014 #include <linux/irqdomain.h>
0015 
0016 #define MAX8997_REG_INVALID (0xff)
0017 
0018 enum max8997_pmic_reg {
0019     MAX8997_REG_PMIC_ID0    = 0x00,
0020     MAX8997_REG_PMIC_ID1    = 0x01,
0021     MAX8997_REG_INTSRC  = 0x02,
0022     MAX8997_REG_INT1    = 0x03,
0023     MAX8997_REG_INT2    = 0x04,
0024     MAX8997_REG_INT3    = 0x05,
0025     MAX8997_REG_INT4    = 0x06,
0026 
0027     MAX8997_REG_INT1MSK = 0x08,
0028     MAX8997_REG_INT2MSK = 0x09,
0029     MAX8997_REG_INT3MSK = 0x0a,
0030     MAX8997_REG_INT4MSK = 0x0b,
0031 
0032     MAX8997_REG_STATUS1 = 0x0d,
0033     MAX8997_REG_STATUS2 = 0x0e,
0034     MAX8997_REG_STATUS3 = 0x0f,
0035     MAX8997_REG_STATUS4 = 0x10,
0036 
0037     MAX8997_REG_MAINCON1    = 0x13,
0038     MAX8997_REG_MAINCON2    = 0x14,
0039     MAX8997_REG_BUCKRAMP    = 0x15,
0040 
0041     MAX8997_REG_BUCK1CTRL   = 0x18,
0042     MAX8997_REG_BUCK1DVS1   = 0x19,
0043     MAX8997_REG_BUCK1DVS2   = 0x1a,
0044     MAX8997_REG_BUCK1DVS3   = 0x1b,
0045     MAX8997_REG_BUCK1DVS4   = 0x1c,
0046     MAX8997_REG_BUCK1DVS5   = 0x1d,
0047     MAX8997_REG_BUCK1DVS6   = 0x1e,
0048     MAX8997_REG_BUCK1DVS7   = 0x1f,
0049     MAX8997_REG_BUCK1DVS8   = 0x20,
0050     MAX8997_REG_BUCK2CTRL   = 0x21,
0051     MAX8997_REG_BUCK2DVS1   = 0x22,
0052     MAX8997_REG_BUCK2DVS2   = 0x23,
0053     MAX8997_REG_BUCK2DVS3   = 0x24,
0054     MAX8997_REG_BUCK2DVS4   = 0x25,
0055     MAX8997_REG_BUCK2DVS5   = 0x26,
0056     MAX8997_REG_BUCK2DVS6   = 0x27,
0057     MAX8997_REG_BUCK2DVS7   = 0x28,
0058     MAX8997_REG_BUCK2DVS8   = 0x29,
0059     MAX8997_REG_BUCK3CTRL   = 0x2a,
0060     MAX8997_REG_BUCK3DVS    = 0x2b,
0061     MAX8997_REG_BUCK4CTRL   = 0x2c,
0062     MAX8997_REG_BUCK4DVS    = 0x2d,
0063     MAX8997_REG_BUCK5CTRL   = 0x2e,
0064     MAX8997_REG_BUCK5DVS1   = 0x2f,
0065     MAX8997_REG_BUCK5DVS2   = 0x30,
0066     MAX8997_REG_BUCK5DVS3   = 0x31,
0067     MAX8997_REG_BUCK5DVS4   = 0x32,
0068     MAX8997_REG_BUCK5DVS5   = 0x33,
0069     MAX8997_REG_BUCK5DVS6   = 0x34,
0070     MAX8997_REG_BUCK5DVS7   = 0x35,
0071     MAX8997_REG_BUCK5DVS8   = 0x36,
0072     MAX8997_REG_BUCK6CTRL   = 0x37,
0073     MAX8997_REG_BUCK6BPSKIPCTRL = 0x38,
0074     MAX8997_REG_BUCK7CTRL   = 0x39,
0075     MAX8997_REG_BUCK7DVS    = 0x3a,
0076     MAX8997_REG_LDO1CTRL    = 0x3b,
0077     MAX8997_REG_LDO2CTRL    = 0x3c,
0078     MAX8997_REG_LDO3CTRL    = 0x3d,
0079     MAX8997_REG_LDO4CTRL    = 0x3e,
0080     MAX8997_REG_LDO5CTRL    = 0x3f,
0081     MAX8997_REG_LDO6CTRL    = 0x40,
0082     MAX8997_REG_LDO7CTRL    = 0x41,
0083     MAX8997_REG_LDO8CTRL    = 0x42,
0084     MAX8997_REG_LDO9CTRL    = 0x43,
0085     MAX8997_REG_LDO10CTRL   = 0x44,
0086     MAX8997_REG_LDO11CTRL   = 0x45,
0087     MAX8997_REG_LDO12CTRL   = 0x46,
0088     MAX8997_REG_LDO13CTRL   = 0x47,
0089     MAX8997_REG_LDO14CTRL   = 0x48,
0090     MAX8997_REG_LDO15CTRL   = 0x49,
0091     MAX8997_REG_LDO16CTRL   = 0x4a,
0092     MAX8997_REG_LDO17CTRL   = 0x4b,
0093     MAX8997_REG_LDO18CTRL   = 0x4c,
0094     MAX8997_REG_LDO21CTRL   = 0x4d,
0095 
0096     MAX8997_REG_MBCCTRL1    = 0x50,
0097     MAX8997_REG_MBCCTRL2    = 0x51,
0098     MAX8997_REG_MBCCTRL3    = 0x52,
0099     MAX8997_REG_MBCCTRL4    = 0x53,
0100     MAX8997_REG_MBCCTRL5    = 0x54,
0101     MAX8997_REG_MBCCTRL6    = 0x55,
0102     MAX8997_REG_OTPCGHCVS   = 0x56,
0103 
0104     MAX8997_REG_SAFEOUTCTRL = 0x5a,
0105 
0106     MAX8997_REG_LBCNFG1 = 0x5e,
0107     MAX8997_REG_LBCNFG2 = 0x5f,
0108     MAX8997_REG_BBCCTRL = 0x60,
0109 
0110     MAX8997_REG_FLASH1_CUR  = 0x63, /* 0x63 ~ 0x6e for FLASH */
0111     MAX8997_REG_FLASH2_CUR  = 0x64,
0112     MAX8997_REG_MOVIE_CUR   = 0x65,
0113     MAX8997_REG_GSMB_CUR    = 0x66,
0114     MAX8997_REG_BOOST_CNTL  = 0x67,
0115     MAX8997_REG_LEN_CNTL    = 0x68,
0116     MAX8997_REG_FLASH_CNTL  = 0x69,
0117     MAX8997_REG_WDT_CNTL    = 0x6a,
0118     MAX8997_REG_MAXFLASH1   = 0x6b,
0119     MAX8997_REG_MAXFLASH2   = 0x6c,
0120     MAX8997_REG_FLASHSTATUS = 0x6d,
0121     MAX8997_REG_FLASHSTATUSMASK = 0x6e,
0122 
0123     MAX8997_REG_GPIOCNTL1   = 0x70,
0124     MAX8997_REG_GPIOCNTL2   = 0x71,
0125     MAX8997_REG_GPIOCNTL3   = 0x72,
0126     MAX8997_REG_GPIOCNTL4   = 0x73,
0127     MAX8997_REG_GPIOCNTL5   = 0x74,
0128     MAX8997_REG_GPIOCNTL6   = 0x75,
0129     MAX8997_REG_GPIOCNTL7   = 0x76,
0130     MAX8997_REG_GPIOCNTL8   = 0x77,
0131     MAX8997_REG_GPIOCNTL9   = 0x78,
0132     MAX8997_REG_GPIOCNTL10  = 0x79,
0133     MAX8997_REG_GPIOCNTL11  = 0x7a,
0134     MAX8997_REG_GPIOCNTL12  = 0x7b,
0135 
0136     MAX8997_REG_LDO1CONFIG  = 0x80,
0137     MAX8997_REG_LDO2CONFIG  = 0x81,
0138     MAX8997_REG_LDO3CONFIG  = 0x82,
0139     MAX8997_REG_LDO4CONFIG  = 0x83,
0140     MAX8997_REG_LDO5CONFIG  = 0x84,
0141     MAX8997_REG_LDO6CONFIG  = 0x85,
0142     MAX8997_REG_LDO7CONFIG  = 0x86,
0143     MAX8997_REG_LDO8CONFIG  = 0x87,
0144     MAX8997_REG_LDO9CONFIG  = 0x88,
0145     MAX8997_REG_LDO10CONFIG = 0x89,
0146     MAX8997_REG_LDO11CONFIG = 0x8a,
0147     MAX8997_REG_LDO12CONFIG = 0x8b,
0148     MAX8997_REG_LDO13CONFIG = 0x8c,
0149     MAX8997_REG_LDO14CONFIG = 0x8d,
0150     MAX8997_REG_LDO15CONFIG = 0x8e,
0151     MAX8997_REG_LDO16CONFIG = 0x8f,
0152     MAX8997_REG_LDO17CONFIG = 0x90,
0153     MAX8997_REG_LDO18CONFIG = 0x91,
0154     MAX8997_REG_LDO21CONFIG = 0x92,
0155 
0156     MAX8997_REG_DVSOKTIMER1 = 0x97,
0157     MAX8997_REG_DVSOKTIMER2 = 0x98,
0158     MAX8997_REG_DVSOKTIMER4 = 0x99,
0159     MAX8997_REG_DVSOKTIMER5 = 0x9a,
0160 
0161     MAX8997_REG_PMIC_END    = 0x9b,
0162 };
0163 
0164 enum max8997_muic_reg {
0165     MAX8997_MUIC_REG_ID     = 0x0,
0166     MAX8997_MUIC_REG_INT1       = 0x1,
0167     MAX8997_MUIC_REG_INT2       = 0x2,
0168     MAX8997_MUIC_REG_INT3       = 0x3,
0169     MAX8997_MUIC_REG_STATUS1    = 0x4,
0170     MAX8997_MUIC_REG_STATUS2    = 0x5,
0171     MAX8997_MUIC_REG_STATUS3    = 0x6,
0172     MAX8997_MUIC_REG_INTMASK1   = 0x7,
0173     MAX8997_MUIC_REG_INTMASK2   = 0x8,
0174     MAX8997_MUIC_REG_INTMASK3   = 0x9,
0175     MAX8997_MUIC_REG_CDETCTRL   = 0xa,
0176 
0177     MAX8997_MUIC_REG_CONTROL1   = 0xc,
0178     MAX8997_MUIC_REG_CONTROL2   = 0xd,
0179     MAX8997_MUIC_REG_CONTROL3   = 0xe,
0180 
0181     MAX8997_MUIC_REG_END        = 0xf,
0182 };
0183 
0184 /* MAX8997-MUIC STATUS1 register */
0185 #define STATUS1_ADC_SHIFT       0
0186 #define STATUS1_ADCLOW_SHIFT        5
0187 #define STATUS1_ADCERR_SHIFT        6
0188 #define STATUS1_ADC_MASK        (0x1f << STATUS1_ADC_SHIFT)
0189 #define STATUS1_ADCLOW_MASK     (0x1 << STATUS1_ADCLOW_SHIFT)
0190 #define STATUS1_ADCERR_MASK     (0x1 << STATUS1_ADCERR_SHIFT)
0191 
0192 /* MAX8997-MUIC STATUS2 register */
0193 #define STATUS2_CHGTYP_SHIFT        0
0194 #define STATUS2_CHGDETRUN_SHIFT     3
0195 #define STATUS2_DCDTMR_SHIFT        4
0196 #define STATUS2_DBCHG_SHIFT     5
0197 #define STATUS2_VBVOLT_SHIFT        6
0198 #define STATUS2_CHGTYP_MASK     (0x7 << STATUS2_CHGTYP_SHIFT)
0199 #define STATUS2_CHGDETRUN_MASK      (0x1 << STATUS2_CHGDETRUN_SHIFT)
0200 #define STATUS2_DCDTMR_MASK     (0x1 << STATUS2_DCDTMR_SHIFT)
0201 #define STATUS2_DBCHG_MASK      (0x1 << STATUS2_DBCHG_SHIFT)
0202 #define STATUS2_VBVOLT_MASK     (0x1 << STATUS2_VBVOLT_SHIFT)
0203 
0204 /* MAX8997-MUIC STATUS3 register */
0205 #define STATUS3_OVP_SHIFT       2
0206 #define STATUS3_OVP_MASK        (0x1 << STATUS3_OVP_SHIFT)
0207 
0208 /* MAX8997-MUIC CONTROL1 register */
0209 #define COMN1SW_SHIFT           0
0210 #define COMP2SW_SHIFT           3
0211 #define COMN1SW_MASK            (0x7 << COMN1SW_SHIFT)
0212 #define COMP2SW_MASK            (0x7 << COMP2SW_SHIFT)
0213 #define COMP_SW_MASK        (COMP2SW_MASK | COMN1SW_MASK)
0214 
0215 #define CONTROL1_SW_USB         ((1 << COMP2SW_SHIFT) \
0216                         | (1 << COMN1SW_SHIFT))
0217 #define CONTROL1_SW_AUDIO       ((2 << COMP2SW_SHIFT) \
0218                         | (2 << COMN1SW_SHIFT))
0219 #define CONTROL1_SW_UART        ((3 << COMP2SW_SHIFT) \
0220                         | (3 << COMN1SW_SHIFT))
0221 #define CONTROL1_SW_OPEN        ((0 << COMP2SW_SHIFT) \
0222                         | (0 << COMN1SW_SHIFT))
0223 
0224 #define CONTROL2_LOWPWR_SHIFT       (0)
0225 #define CONTROL2_ADCEN_SHIFT        (1)
0226 #define CONTROL2_CPEN_SHIFT     (2)
0227 #define CONTROL2_SFOUTASRT_SHIFT    (3)
0228 #define CONTROL2_SFOUTORD_SHIFT     (4)
0229 #define CONTROL2_ACCDET_SHIFT       (5)
0230 #define CONTROL2_USBCPINT_SHIFT     (6)
0231 #define CONTROL2_RCPS_SHIFT     (7)
0232 #define CONTROL2_LOWPWR_MASK        (0x1 << CONTROL2_LOWPWR_SHIFT)
0233 #define CONTROL2_ADCEN_MASK     (0x1 << CONTROL2_ADCEN_SHIFT)
0234 #define CONTROL2_CPEN_MASK      (0x1 << CONTROL2_CPEN_SHIFT)
0235 #define CONTROL2_SFOUTASRT_MASK     (0x1 << CONTROL2_SFOUTASRT_SHIFT)
0236 #define CONTROL2_SFOUTORD_MASK      (0x1 << CONTROL2_SFOUTORD_SHIFT)
0237 #define CONTROL2_ACCDET_MASK        (0x1 << CONTROL2_ACCDET_SHIFT)
0238 #define CONTROL2_USBCPINT_MASK      (0x1 << CONTROL2_USBCPINT_SHIFT)
0239 #define CONTROL2_RCPS_MASK      (0x1 << CONTROL2_RCPS_SHIFT)
0240 
0241 #define CONTROL3_JIGSET_SHIFT       (0)
0242 #define CONTROL3_BTLDSET_SHIFT      (2)
0243 #define CONTROL3_ADCDBSET_SHIFT     (4)
0244 #define CONTROL3_JIGSET_MASK        (0x3 << CONTROL3_JIGSET_SHIFT)
0245 #define CONTROL3_BTLDSET_MASK       (0x3 << CONTROL3_BTLDSET_SHIFT)
0246 #define CONTROL3_ADCDBSET_MASK      (0x3 << CONTROL3_ADCDBSET_SHIFT)
0247 
0248 enum max8997_haptic_reg {
0249     MAX8997_HAPTIC_REG_GENERAL  = 0x00,
0250     MAX8997_HAPTIC_REG_CONF1    = 0x01,
0251     MAX8997_HAPTIC_REG_CONF2    = 0x02,
0252     MAX8997_HAPTIC_REG_DRVCONF  = 0x03,
0253     MAX8997_HAPTIC_REG_CYCLECONF1   = 0x04,
0254     MAX8997_HAPTIC_REG_CYCLECONF2   = 0x05,
0255     MAX8997_HAPTIC_REG_SIGCONF1 = 0x06,
0256     MAX8997_HAPTIC_REG_SIGCONF2 = 0x07,
0257     MAX8997_HAPTIC_REG_SIGCONF3 = 0x08,
0258     MAX8997_HAPTIC_REG_SIGCONF4 = 0x09,
0259     MAX8997_HAPTIC_REG_SIGDC1   = 0x0a,
0260     MAX8997_HAPTIC_REG_SIGDC2   = 0x0b,
0261     MAX8997_HAPTIC_REG_SIGPWMDC1    = 0x0c,
0262     MAX8997_HAPTIC_REG_SIGPWMDC2    = 0x0d,
0263     MAX8997_HAPTIC_REG_SIGPWMDC3    = 0x0e,
0264     MAX8997_HAPTIC_REG_SIGPWMDC4    = 0x0f,
0265     MAX8997_HAPTIC_REG_MTR_REV  = 0x10,
0266 
0267     MAX8997_HAPTIC_REG_END      = 0x11,
0268 };
0269 
0270 /* slave addr = 0x0c: using "2nd part" of rev4 datasheet */
0271 enum max8997_rtc_reg {
0272     MAX8997_RTC_CTRLMASK        = 0x02,
0273     MAX8997_RTC_CTRL        = 0x03,
0274     MAX8997_RTC_UPDATE1     = 0x04,
0275     MAX8997_RTC_UPDATE2     = 0x05,
0276     MAX8997_RTC_WTSR_SMPL       = 0x06,
0277 
0278     MAX8997_RTC_SEC         = 0x10,
0279     MAX8997_RTC_MIN         = 0x11,
0280     MAX8997_RTC_HOUR        = 0x12,
0281     MAX8997_RTC_DAY_OF_WEEK     = 0x13,
0282     MAX8997_RTC_MONTH       = 0x14,
0283     MAX8997_RTC_YEAR        = 0x15,
0284     MAX8997_RTC_DAY_OF_MONTH    = 0x16,
0285     MAX8997_RTC_ALARM1_SEC      = 0x17,
0286     MAX8997_RTC_ALARM1_MIN      = 0x18,
0287     MAX8997_RTC_ALARM1_HOUR     = 0x19,
0288     MAX8997_RTC_ALARM1_DAY_OF_WEEK  = 0x1a,
0289     MAX8997_RTC_ALARM1_MONTH    = 0x1b,
0290     MAX8997_RTC_ALARM1_YEAR     = 0x1c,
0291     MAX8997_RTC_ALARM1_DAY_OF_MONTH = 0x1d,
0292     MAX8997_RTC_ALARM2_SEC      = 0x1e,
0293     MAX8997_RTC_ALARM2_MIN      = 0x1f,
0294     MAX8997_RTC_ALARM2_HOUR     = 0x20,
0295     MAX8997_RTC_ALARM2_DAY_OF_WEEK  = 0x21,
0296     MAX8997_RTC_ALARM2_MONTH    = 0x22,
0297     MAX8997_RTC_ALARM2_YEAR     = 0x23,
0298     MAX8997_RTC_ALARM2_DAY_OF_MONTH = 0x24,
0299 };
0300 
0301 enum max8997_irq_source {
0302     PMIC_INT1 = 0,
0303     PMIC_INT2,
0304     PMIC_INT3,
0305     PMIC_INT4,
0306 
0307     FUEL_GAUGE, /* Ignored (MAX17042 driver handles) */
0308 
0309     MUIC_INT1,
0310     MUIC_INT2,
0311     MUIC_INT3,
0312 
0313     GPIO_LOW, /* Not implemented */
0314     GPIO_HI, /* Not implemented */
0315 
0316     FLASH_STATUS, /* Not implemented */
0317 
0318     MAX8997_IRQ_GROUP_NR,
0319 };
0320 
0321 enum max8997_irq {
0322     MAX8997_PMICIRQ_PWRONR,
0323     MAX8997_PMICIRQ_PWRONF,
0324     MAX8997_PMICIRQ_PWRON1SEC,
0325     MAX8997_PMICIRQ_JIGONR,
0326     MAX8997_PMICIRQ_JIGONF,
0327     MAX8997_PMICIRQ_LOWBAT2,
0328     MAX8997_PMICIRQ_LOWBAT1,
0329 
0330     MAX8997_PMICIRQ_JIGR,
0331     MAX8997_PMICIRQ_JIGF,
0332     MAX8997_PMICIRQ_MR,
0333     MAX8997_PMICIRQ_DVS1OK,
0334     MAX8997_PMICIRQ_DVS2OK,
0335     MAX8997_PMICIRQ_DVS3OK,
0336     MAX8997_PMICIRQ_DVS4OK,
0337 
0338     MAX8997_PMICIRQ_CHGINS,
0339     MAX8997_PMICIRQ_CHGRM,
0340     MAX8997_PMICIRQ_DCINOVP,
0341     MAX8997_PMICIRQ_TOPOFFR,
0342     MAX8997_PMICIRQ_CHGRSTF,
0343     MAX8997_PMICIRQ_MBCHGTMEXPD,
0344 
0345     MAX8997_PMICIRQ_RTC60S,
0346     MAX8997_PMICIRQ_RTCA1,
0347     MAX8997_PMICIRQ_RTCA2,
0348     MAX8997_PMICIRQ_SMPL_INT,
0349     MAX8997_PMICIRQ_RTC1S,
0350     MAX8997_PMICIRQ_WTSR,
0351 
0352     MAX8997_MUICIRQ_ADCError,
0353     MAX8997_MUICIRQ_ADCLow,
0354     MAX8997_MUICIRQ_ADC,
0355 
0356     MAX8997_MUICIRQ_VBVolt,
0357     MAX8997_MUICIRQ_DBChg,
0358     MAX8997_MUICIRQ_DCDTmr,
0359     MAX8997_MUICIRQ_ChgDetRun,
0360     MAX8997_MUICIRQ_ChgTyp,
0361 
0362     MAX8997_MUICIRQ_OVP,
0363 
0364     MAX8997_IRQ_NR,
0365 };
0366 
0367 #define MAX8997_NUM_GPIO    12
0368 struct max8997_dev {
0369     struct device *dev;
0370     struct max8997_platform_data *pdata;
0371     struct i2c_client *i2c; /* 0xcc / PMIC, Battery Control, and FLASH */
0372     struct i2c_client *rtc; /* slave addr 0x0c */
0373     struct i2c_client *haptic; /* slave addr 0x90 */
0374     struct i2c_client *muic; /* slave addr 0x4a */
0375     struct mutex iolock;
0376 
0377     unsigned long type;
0378     struct platform_device *battery; /* battery control (not fuel gauge) */
0379 
0380     int irq;
0381     int ono;
0382     struct irq_domain *irq_domain;
0383     struct mutex irqlock;
0384     int irq_masks_cur[MAX8997_IRQ_GROUP_NR];
0385     int irq_masks_cache[MAX8997_IRQ_GROUP_NR];
0386 
0387     /* For hibernation */
0388     u8 reg_dump[MAX8997_REG_PMIC_END + MAX8997_MUIC_REG_END +
0389         MAX8997_HAPTIC_REG_END];
0390 
0391     bool gpio_status[MAX8997_NUM_GPIO];
0392 };
0393 
0394 enum max8997_types {
0395     TYPE_MAX8997,
0396     TYPE_MAX8966,
0397 };
0398 
0399 extern int max8997_irq_init(struct max8997_dev *max8997);
0400 extern void max8997_irq_exit(struct max8997_dev *max8997);
0401 extern int max8997_irq_resume(struct max8997_dev *max8997);
0402 
0403 extern int max8997_read_reg(struct i2c_client *i2c, u8 reg, u8 *dest);
0404 extern int max8997_bulk_read(struct i2c_client *i2c, u8 reg, int count,
0405                 u8 *buf);
0406 extern int max8997_write_reg(struct i2c_client *i2c, u8 reg, u8 value);
0407 extern int max8997_bulk_write(struct i2c_client *i2c, u8 reg, int count,
0408                 u8 *buf);
0409 extern int max8997_update_reg(struct i2c_client *i2c, u8 reg, u8 val, u8 mask);
0410 
0411 #define MAX8997_GPIO_INT_BOTH   (0x3 << 4)
0412 #define MAX8997_GPIO_INT_RISE   (0x2 << 4)
0413 #define MAX8997_GPIO_INT_FALL   (0x1 << 4)
0414 
0415 #define MAX8997_GPIO_INT_MASK   (0x3 << 4)
0416 #define MAX8997_GPIO_DATA_MASK  (0x1 << 2)
0417 #endif /*  __LINUX_MFD_MAX8997_PRIV_H */
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