linux/mfd/max14577-private.h

0001 /* SPDX-License-Identifier: GPL-2.0+ */
0002 /*
0003  * max14577-private.h - Common API for the Maxim 14577/77836 internal sub chip
0004  *
0005  * Copyright (C) 2014 Samsung Electrnoics
0006  * Chanwoo Choi <cw00.choi@samsung.com>
0007  * Krzysztof Kozlowski <krzk@kernel.org>
0008  */
0009
0010 #ifndef __MAX14577_PRIVATE_H__
0011 #define __MAX14577_PRIVATE_H__
0012
0013 #include <linux/i2c.h>
0014 #include <linux/regmap.h>
0015
0016 #define I2C_ADDR_PMIC   (0x46 >> 1)
0017 #define I2C_ADDR_MUIC   (0x4A >> 1)
0018 #define I2C_ADDR_FG (0x6C >> 1)
0019
0020 enum maxim_device_type {
0021     MAXIM_DEVICE_TYPE_UNKNOWN   = 0,
0022     MAXIM_DEVICE_TYPE_MAX14577,
0023     MAXIM_DEVICE_TYPE_MAX77836,
0024
0025     MAXIM_DEVICE_TYPE_NUM,
0026 };
0027
0028 /* Slave addr = 0x4A: MUIC and Charger */
0029 enum max14577_reg {
0030     MAX14577_REG_DEVICEID       = 0x00,
0031     MAX14577_REG_INT1       = 0x01,
0032     MAX14577_REG_INT2       = 0x02,
0033     MAX14577_REG_INT3       = 0x03,
0034     MAX14577_REG_STATUS1        = 0x04,
0035     MAX14577_REG_STATUS2        = 0x05,
0036     MAX14577_REG_STATUS3        = 0x06,
0037     MAX14577_REG_INTMASK1       = 0x07,
0038     MAX14577_REG_INTMASK2       = 0x08,
0039     MAX14577_REG_INTMASK3       = 0x09,
0040     MAX14577_REG_CDETCTRL1      = 0x0A,
0041     MAX14577_REG_RFU        = 0x0B,
0042     MAX14577_REG_CONTROL1       = 0x0C,
0043     MAX14577_REG_CONTROL2       = 0x0D,
0044     MAX14577_REG_CONTROL3       = 0x0E,
0045     MAX14577_REG_CHGCTRL1       = 0x0F,
0046     MAX14577_REG_CHGCTRL2       = 0x10,
0047     MAX14577_REG_CHGCTRL3       = 0x11,
0048     MAX14577_REG_CHGCTRL4       = 0x12,
0049     MAX14577_REG_CHGCTRL5       = 0x13,
0050     MAX14577_REG_CHGCTRL6       = 0x14,
0051     MAX14577_REG_CHGCTRL7       = 0x15,
0052
0053     MAX14577_REG_END,
0054 };
0055
0056 /* Slave addr = 0x4A: MUIC */
0057 enum max14577_muic_reg {
0058     MAX14577_MUIC_REG_STATUS1   = 0x04,
0059     MAX14577_MUIC_REG_STATUS2   = 0x05,
0060     MAX14577_MUIC_REG_CONTROL1  = 0x0C,
0061     MAX14577_MUIC_REG_CONTROL3  = 0x0E,
0062
0063     MAX14577_MUIC_REG_END,
0064 };
0065
0066 /*
0067  * Combined charger types for max14577 and max77836.
0068  *
0069  * On max14577 three lower bits map to STATUS2/CHGTYP field.
0070  * However the max77836 has different two last values of STATUS2/CHGTYP.
0071  * To indicate the difference enum has two additional values for max77836.
0072  * These values are just a register value bitwise OR with 0x8.
0073  */
0074 enum max14577_muic_charger_type {
0075     MAX14577_CHARGER_TYPE_NONE      = 0x0,
0076     MAX14577_CHARGER_TYPE_USB       = 0x1,
0077     MAX14577_CHARGER_TYPE_DOWNSTREAM_PORT   = 0x2,
0078     MAX14577_CHARGER_TYPE_DEDICATED_CHG = 0x3,
0079     MAX14577_CHARGER_TYPE_SPECIAL_500MA = 0x4,
0080     /* Special 1A or 2A charger */
0081     MAX14577_CHARGER_TYPE_SPECIAL_1A    = 0x5,
0082     /* max14577: reserved, used on max77836 */
0083     MAX14577_CHARGER_TYPE_RESERVED      = 0x6,
0084     /* max14577: dead-battery charing with maximum current 100mA */
0085     MAX14577_CHARGER_TYPE_DEAD_BATTERY  = 0x7,
0086     /*
0087      * max77836: special charger (bias on D+/D-),
0088      * matches register value of 0x6
0089      */
0090     MAX77836_CHARGER_TYPE_SPECIAL_BIAS  = 0xe,
0091     /* max77836: reserved, register value 0x7 */
0092     MAX77836_CHARGER_TYPE_RESERVED      = 0xf,
0093 };
0094
0095 /* MAX14577 interrupts */
0096 #define MAX14577_INT1_ADC_MASK      BIT(0)
0097 #define MAX14577_INT1_ADCLOW_MASK   BIT(1)
0098 #define MAX14577_INT1_ADCERR_MASK   BIT(2)
0099 #define MAX77836_INT1_ADC1K_MASK    BIT(3)
0100
0101 #define MAX14577_INT2_CHGTYP_MASK   BIT(0)
0102 #define MAX14577_INT2_CHGDETRUN_MASK    BIT(1)
0103 #define MAX14577_INT2_DCDTMR_MASK   BIT(2)
0104 #define MAX14577_INT2_DBCHG_MASK    BIT(3)
0105 #define MAX14577_INT2_VBVOLT_MASK   BIT(4)
0106 #define MAX77836_INT2_VIDRM_MASK    BIT(5)
0107
0108 #define MAX14577_INT3_EOC_MASK      BIT(0)
0109 #define MAX14577_INT3_CGMBC_MASK    BIT(1)
0110 #define MAX14577_INT3_OVP_MASK      BIT(2)
0111 #define MAX14577_INT3_MBCCHGERR_MASK    BIT(3)
0112
0113 /* MAX14577 DEVICE ID register */
0114 #define DEVID_VENDORID_SHIFT        0
0115 #define DEVID_DEVICEID_SHIFT        3
0116 #define DEVID_VENDORID_MASK     (0x07 << DEVID_VENDORID_SHIFT)
0117 #define DEVID_DEVICEID_MASK     (0x1f << DEVID_DEVICEID_SHIFT)
0118
0119 /* MAX14577 STATUS1 register */
0120 #define STATUS1_ADC_SHIFT       0
0121 #define STATUS1_ADCLOW_SHIFT        5
0122 #define STATUS1_ADCERR_SHIFT        6
0123 #define MAX77836_STATUS1_ADC1K_SHIFT    7
0124 #define STATUS1_ADC_MASK        (0x1f << STATUS1_ADC_SHIFT)
0125 #define STATUS1_ADCLOW_MASK     BIT(STATUS1_ADCLOW_SHIFT)
0126 #define STATUS1_ADCERR_MASK     BIT(STATUS1_ADCERR_SHIFT)
0127 #define MAX77836_STATUS1_ADC1K_MASK BIT(MAX77836_STATUS1_ADC1K_SHIFT)
0128
0129 /* MAX14577 STATUS2 register */
0130 #define STATUS2_CHGTYP_SHIFT        0
0131 #define STATUS2_CHGDETRUN_SHIFT     3
0132 #define STATUS2_DCDTMR_SHIFT        4
0133 #define MAX14577_STATUS2_DBCHG_SHIFT    5
0134 #define MAX77836_STATUS2_DXOVP_SHIFT    5
0135 #define STATUS2_VBVOLT_SHIFT        6
0136 #define MAX77836_STATUS2_VIDRM_SHIFT    7
0137 #define STATUS2_CHGTYP_MASK     (0x7 << STATUS2_CHGTYP_SHIFT)
0138 #define STATUS2_CHGDETRUN_MASK      BIT(STATUS2_CHGDETRUN_SHIFT)
0139 #define STATUS2_DCDTMR_MASK     BIT(STATUS2_DCDTMR_SHIFT)
0140 #define MAX14577_STATUS2_DBCHG_MASK BIT(MAX14577_STATUS2_DBCHG_SHIFT)
0141 #define MAX77836_STATUS2_DXOVP_MASK BIT(MAX77836_STATUS2_DXOVP_SHIFT)
0142 #define STATUS2_VBVOLT_MASK     BIT(STATUS2_VBVOLT_SHIFT)
0143 #define MAX77836_STATUS2_VIDRM_MASK BIT(MAX77836_STATUS2_VIDRM_SHIFT)
0144
0145 /* MAX14577 CONTROL1 register */
0146 #define COMN1SW_SHIFT           0
0147 #define COMP2SW_SHIFT           3
0148 #define MICEN_SHIFT         6
0149 #define IDBEN_SHIFT         7
0150 #define COMN1SW_MASK            (0x7 << COMN1SW_SHIFT)
0151 #define COMP2SW_MASK            (0x7 << COMP2SW_SHIFT)
0152 #define MICEN_MASK          BIT(MICEN_SHIFT)
0153 #define IDBEN_MASK          BIT(IDBEN_SHIFT)
0154 #define CLEAR_IDBEN_MICEN_MASK      (COMN1SW_MASK | COMP2SW_MASK)
0155 #define CTRL1_SW_USB            ((1 << COMP2SW_SHIFT) \
0156                         | (1 << COMN1SW_SHIFT))
0157 #define CTRL1_SW_AUDIO          ((2 << COMP2SW_SHIFT) \
0158                         | (2 << COMN1SW_SHIFT))
0159 #define CTRL1_SW_UART           ((3 << COMP2SW_SHIFT) \
0160                         | (3 << COMN1SW_SHIFT))
0161 #define CTRL1_SW_OPEN           ((0 << COMP2SW_SHIFT) \
0162                         | (0 << COMN1SW_SHIFT))
0163
0164 /* MAX14577 CONTROL2 register */
0165 #define CTRL2_LOWPWR_SHIFT      (0)
0166 #define CTRL2_ADCEN_SHIFT       (1)
0167 #define CTRL2_CPEN_SHIFT        (2)
0168 #define CTRL2_SFOUTASRT_SHIFT       (3)
0169 #define CTRL2_SFOUTORD_SHIFT        (4)
0170 #define CTRL2_ACCDET_SHIFT      (5)
0171 #define CTRL2_USBCPINT_SHIFT        (6)
0172 #define CTRL2_RCPS_SHIFT        (7)
0173 #define CTRL2_LOWPWR_MASK       BIT(CTRL2_LOWPWR_SHIFT)
0174 #define CTRL2_ADCEN_MASK        BIT(CTRL2_ADCEN_SHIFT)
0175 #define CTRL2_CPEN_MASK         BIT(CTRL2_CPEN_SHIFT)
0176 #define CTRL2_SFOUTASRT_MASK        BIT(CTRL2_SFOUTASRT_SHIFT)
0177 #define CTRL2_SFOUTORD_MASK     BIT(CTRL2_SFOUTORD_SHIFT)
0178 #define CTRL2_ACCDET_MASK       BIT(CTRL2_ACCDET_SHIFT)
0179 #define CTRL2_USBCPINT_MASK     BIT(CTRL2_USBCPINT_SHIFT)
0180 #define CTRL2_RCPS_MASK         BIT(CTRL2_RCPS_SHIFT)
0181
0182 #define CTRL2_CPEN1_LOWPWR0 ((1 << CTRL2_CPEN_SHIFT) | \
0183                 (0 << CTRL2_LOWPWR_SHIFT))
0184 #define CTRL2_CPEN0_LOWPWR1 ((0 << CTRL2_CPEN_SHIFT) | \
0185                 (1 << CTRL2_LOWPWR_SHIFT))
0186
0187 /* MAX14577 CONTROL3 register */
0188 #define CTRL3_JIGSET_SHIFT      0
0189 #define CTRL3_BOOTSET_SHIFT     2
0190 #define CTRL3_ADCDBSET_SHIFT        4
0191 #define CTRL3_WBTH_SHIFT        6
0192 #define CTRL3_JIGSET_MASK       (0x3 << CTRL3_JIGSET_SHIFT)
0193 #define CTRL3_BOOTSET_MASK      (0x3 << CTRL3_BOOTSET_SHIFT)
0194 #define CTRL3_ADCDBSET_MASK     (0x3 << CTRL3_ADCDBSET_SHIFT)
0195 #define CTRL3_WBTH_MASK         (0x3 << CTRL3_WBTH_SHIFT)
0196
0197 /* Slave addr = 0x4A: Charger */
0198 enum max14577_charger_reg {
0199     MAX14577_CHG_REG_STATUS3    = 0x06,
0200     MAX14577_CHG_REG_CHG_CTRL1  = 0x0F,
0201     MAX14577_CHG_REG_CHG_CTRL2  = 0x10,
0202     MAX14577_CHG_REG_CHG_CTRL3  = 0x11,
0203     MAX14577_CHG_REG_CHG_CTRL4  = 0x12,
0204     MAX14577_CHG_REG_CHG_CTRL5  = 0x13,
0205     MAX14577_CHG_REG_CHG_CTRL6  = 0x14,
0206     MAX14577_CHG_REG_CHG_CTRL7  = 0x15,
0207
0208     MAX14577_CHG_REG_END,
0209 };
0210
0211 /* MAX14577 STATUS3 register */
0212 #define STATUS3_EOC_SHIFT       0
0213 #define STATUS3_CGMBC_SHIFT     1
0214 #define STATUS3_OVP_SHIFT       2
0215 #define STATUS3_MBCCHGERR_SHIFT     3
0216 #define STATUS3_EOC_MASK        (0x1 << STATUS3_EOC_SHIFT)
0217 #define STATUS3_CGMBC_MASK      (0x1 << STATUS3_CGMBC_SHIFT)
0218 #define STATUS3_OVP_MASK        (0x1 << STATUS3_OVP_SHIFT)
0219 #define STATUS3_MBCCHGERR_MASK      (0x1 << STATUS3_MBCCHGERR_SHIFT)
0220
0221 /* MAX14577 CDETCTRL1 register */
0222 #define CDETCTRL1_CHGDETEN_SHIFT    0
0223 #define CDETCTRL1_CHGTYPMAN_SHIFT   1
0224 #define CDETCTRL1_DCDEN_SHIFT       2
0225 #define CDETCTRL1_DCD2SCT_SHIFT     3
0226 #define MAX14577_CDETCTRL1_DCHKTM_SHIFT 4
0227 #define MAX77836_CDETCTRL1_CDLY_SHIFT   4
0228 #define MAX14577_CDETCTRL1_DBEXIT_SHIFT 5
0229 #define MAX77836_CDETCTRL1_DCDCPL_SHIFT 5
0230 #define CDETCTRL1_DBIDLE_SHIFT      6
0231 #define CDETCTRL1_CDPDET_SHIFT      7
0232 #define CDETCTRL1_CHGDETEN_MASK     BIT(CDETCTRL1_CHGDETEN_SHIFT)
0233 #define CDETCTRL1_CHGTYPMAN_MASK    BIT(CDETCTRL1_CHGTYPMAN_SHIFT)
0234 #define CDETCTRL1_DCDEN_MASK        BIT(CDETCTRL1_DCDEN_SHIFT)
0235 #define CDETCTRL1_DCD2SCT_MASK      BIT(CDETCTRL1_DCD2SCT_SHIFT)
0236 #define MAX14577_CDETCTRL1_DCHKTM_MASK  BIT(MAX14577_CDETCTRL1_DCHKTM_SHIFT)
0237 #define MAX77836_CDETCTRL1_CDDLY_MASK   BIT(MAX77836_CDETCTRL1_CDDLY_SHIFT)
0238 #define MAX14577_CDETCTRL1_DBEXIT_MASK  BIT(MAX14577_CDETCTRL1_DBEXIT_SHIFT)
0239 #define MAX77836_CDETCTRL1_DCDCPL_MASK  BIT(MAX77836_CDETCTRL1_DCDCPL_SHIFT)
0240 #define CDETCTRL1_DBIDLE_MASK       BIT(CDETCTRL1_DBIDLE_SHIFT)
0241 #define CDETCTRL1_CDPDET_MASK       BIT(CDETCTRL1_CDPDET_SHIFT)
0242
0243 /* MAX14577 CHGCTRL1 register */
0244 #define CHGCTRL1_TCHW_SHIFT     4
0245 #define CHGCTRL1_TCHW_MASK      (0x7 << CHGCTRL1_TCHW_SHIFT)
0246
0247 /* MAX14577 CHGCTRL2 register */
0248 #define CHGCTRL2_MBCHOSTEN_SHIFT    6
0249 #define CHGCTRL2_MBCHOSTEN_MASK     BIT(CHGCTRL2_MBCHOSTEN_SHIFT)
0250 #define CHGCTRL2_VCHGR_RC_SHIFT     7
0251 #define CHGCTRL2_VCHGR_RC_MASK      BIT(CHGCTRL2_VCHGR_RC_SHIFT)
0252
0253 /* MAX14577 CHGCTRL3 register */
0254 #define CHGCTRL3_MBCCVWRC_SHIFT     0
0255 #define CHGCTRL3_MBCCVWRC_MASK      (0xf << CHGCTRL3_MBCCVWRC_SHIFT)
0256
0257 /* MAX14577 CHGCTRL4 register */
0258 #define CHGCTRL4_MBCICHWRCH_SHIFT   0
0259 #define CHGCTRL4_MBCICHWRCH_MASK    (0xf << CHGCTRL4_MBCICHWRCH_SHIFT)
0260 #define CHGCTRL4_MBCICHWRCL_SHIFT   4
0261 #define CHGCTRL4_MBCICHWRCL_MASK    BIT(CHGCTRL4_MBCICHWRCL_SHIFT)
0262
0263 /* MAX14577 CHGCTRL5 register */
0264 #define CHGCTRL5_EOCS_SHIFT     0
0265 #define CHGCTRL5_EOCS_MASK      (0xf << CHGCTRL5_EOCS_SHIFT)
0266
0267 /* MAX14577 CHGCTRL6 register */
0268 #define CHGCTRL6_AUTOSTOP_SHIFT     5
0269 #define CHGCTRL6_AUTOSTOP_MASK      BIT(CHGCTRL6_AUTOSTOP_SHIFT)
0270
0271 /* MAX14577 CHGCTRL7 register */
0272 #define CHGCTRL7_OTPCGHCVS_SHIFT    0
0273 #define CHGCTRL7_OTPCGHCVS_MASK     (0x3 << CHGCTRL7_OTPCGHCVS_SHIFT)
0274
0275 /* MAX14577 charger current limits (as in CHGCTRL4 register), uA */
0276 #define MAX14577_CHARGER_CURRENT_LIMIT_MIN       90000U
0277 #define MAX14577_CHARGER_CURRENT_LIMIT_HIGH_START   200000U
0278 #define MAX14577_CHARGER_CURRENT_LIMIT_HIGH_STEP     50000U
0279 #define MAX14577_CHARGER_CURRENT_LIMIT_MAX      950000U
0280
0281 /* MAX77836 charger current limits (as in CHGCTRL4 register), uA */
0282 #define MAX77836_CHARGER_CURRENT_LIMIT_MIN       45000U
0283 #define MAX77836_CHARGER_CURRENT_LIMIT_HIGH_START   100000U
0284 #define MAX77836_CHARGER_CURRENT_LIMIT_HIGH_STEP     25000U
0285 #define MAX77836_CHARGER_CURRENT_LIMIT_MAX      475000U
0286
0287 /*
0288  * MAX14577 charger End-Of-Charge current limits
0289  * (as in CHGCTRL5 register), uA
0290  */
0291 #define MAX14577_CHARGER_EOC_CURRENT_LIMIT_MIN      50000U
0292 #define MAX14577_CHARGER_EOC_CURRENT_LIMIT_STEP     10000U
0293 #define MAX14577_CHARGER_EOC_CURRENT_LIMIT_MAX      200000U
0294
0295 /*
0296  * MAX14577/MAX77836 Battery Constant Voltage
0297  * (as in CHGCTRL3 register), uV
0298  */
0299 #define MAXIM_CHARGER_CONSTANT_VOLTAGE_MIN      4000000U
0300 #define MAXIM_CHARGER_CONSTANT_VOLTAGE_STEP     20000U
0301 #define MAXIM_CHARGER_CONSTANT_VOLTAGE_MAX      4350000U
0302
0303 /* Default value for fast charge timer, in hours */
0304 #define MAXIM_CHARGER_FAST_CHARGE_TIMER_DEFAULT     5
0305
0306 /* MAX14577 regulator SFOUT LDO voltage, fixed, uV */
0307 #define MAX14577_REGULATOR_SAFEOUT_VOLTAGE      4900000
0308
0309 /* MAX77836 regulator LDOx voltage, uV */
0310 #define MAX77836_REGULATOR_LDO_VOLTAGE_MIN      800000
0311 #define MAX77836_REGULATOR_LDO_VOLTAGE_MAX      3950000
0312 #define MAX77836_REGULATOR_LDO_VOLTAGE_STEP     50000
0313 #define MAX77836_REGULATOR_LDO_VOLTAGE_STEPS_NUM    64
0314
0315 /* Slave addr = 0x46: PMIC */
0316 enum max77836_pmic_reg {
0317     MAX77836_PMIC_REG_PMIC_ID       = 0x20,
0318     MAX77836_PMIC_REG_PMIC_REV      = 0x21,
0319     MAX77836_PMIC_REG_INTSRC        = 0x22,
0320     MAX77836_PMIC_REG_INTSRC_MASK       = 0x23,
0321     MAX77836_PMIC_REG_TOPSYS_INT        = 0x24,
0322     MAX77836_PMIC_REG_TOPSYS_INT_MASK   = 0x26,
0323     MAX77836_PMIC_REG_TOPSYS_STAT       = 0x28,
0324     MAX77836_PMIC_REG_MRSTB_CNTL        = 0x2A,
0325     MAX77836_PMIC_REG_LSCNFG        = 0x2B,
0326
0327     MAX77836_LDO_REG_CNFG1_LDO1     = 0x51,
0328     MAX77836_LDO_REG_CNFG2_LDO1     = 0x52,
0329     MAX77836_LDO_REG_CNFG1_LDO2     = 0x53,
0330     MAX77836_LDO_REG_CNFG2_LDO2     = 0x54,
0331     MAX77836_LDO_REG_CNFG_LDO_BIAS      = 0x55,
0332
0333     MAX77836_COMP_REG_COMP1         = 0x60,
0334
0335     MAX77836_PMIC_REG_END,
0336 };
0337
0338 #define MAX77836_INTSRC_MASK_TOP_INT_SHIFT  1
0339 #define MAX77836_INTSRC_MASK_MUIC_CHG_INT_SHIFT 3
0340 #define MAX77836_INTSRC_MASK_TOP_INT_MASK   BIT(MAX77836_INTSRC_MASK_TOP_INT_SHIFT)
0341 #define MAX77836_INTSRC_MASK_MUIC_CHG_INT_MASK  BIT(MAX77836_INTSRC_MASK_MUIC_CHG_INT_SHIFT)
0342
0343 /* MAX77836 PMIC interrupts */
0344 #define MAX77836_TOPSYS_INT_T120C_SHIFT     0
0345 #define MAX77836_TOPSYS_INT_T140C_SHIFT     1
0346 #define MAX77836_TOPSYS_INT_T120C_MASK      BIT(MAX77836_TOPSYS_INT_T120C_SHIFT)
0347 #define MAX77836_TOPSYS_INT_T140C_MASK      BIT(MAX77836_TOPSYS_INT_T140C_SHIFT)
0348
0349 /* LDO1/LDO2 CONFIG1 register */
0350 #define MAX77836_CNFG1_LDO_PWRMD_SHIFT      6
0351 #define MAX77836_CNFG1_LDO_TV_SHIFT     0
0352 #define MAX77836_CNFG1_LDO_PWRMD_MASK       (0x3 << MAX77836_CNFG1_LDO_PWRMD_SHIFT)
0353 #define MAX77836_CNFG1_LDO_TV_MASK      (0x3f << MAX77836_CNFG1_LDO_TV_SHIFT)
0354
0355 /* LDO1/LDO2 CONFIG2 register */
0356 #define MAX77836_CNFG2_LDO_OVCLMPEN_SHIFT   7
0357 #define MAX77836_CNFG2_LDO_ALPMEN_SHIFT     6
0358 #define MAX77836_CNFG2_LDO_COMP_SHIFT       4
0359 #define MAX77836_CNFG2_LDO_POK_SHIFT        3
0360 #define MAX77836_CNFG2_LDO_ADE_SHIFT        1
0361 #define MAX77836_CNFG2_LDO_SS_SHIFT     0
0362 #define MAX77836_CNFG2_LDO_OVCLMPEN_MASK    BIT(MAX77836_CNFG2_LDO_OVCLMPEN_SHIFT)
0363 #define MAX77836_CNFG2_LDO_ALPMEN_MASK      BIT(MAX77836_CNFG2_LDO_ALPMEN_SHIFT)
0364 #define MAX77836_CNFG2_LDO_COMP_MASK        (0x3 << MAX77836_CNFG2_LDO_COMP_SHIFT)
0365 #define MAX77836_CNFG2_LDO_POK_MASK     BIT(MAX77836_CNFG2_LDO_POK_SHIFT)
0366 #define MAX77836_CNFG2_LDO_ADE_MASK     BIT(MAX77836_CNFG2_LDO_ADE_SHIFT)
0367 #define MAX77836_CNFG2_LDO_SS_MASK      BIT(MAX77836_CNFG2_LDO_SS_SHIFT)
0368
0369 /* Slave addr = 0x6C: Fuel-Gauge/Battery */
0370 enum max77836_fg_reg {
0371     MAX77836_FG_REG_VCELL_MSB   = 0x02,
0372     MAX77836_FG_REG_VCELL_LSB   = 0x03,
0373     MAX77836_FG_REG_SOC_MSB     = 0x04,
0374     MAX77836_FG_REG_SOC_LSB     = 0x05,
0375     MAX77836_FG_REG_MODE_H      = 0x06,
0376     MAX77836_FG_REG_MODE_L      = 0x07,
0377     MAX77836_FG_REG_VERSION_MSB = 0x08,
0378     MAX77836_FG_REG_VERSION_LSB = 0x09,
0379     MAX77836_FG_REG_HIBRT_H     = 0x0A,
0380     MAX77836_FG_REG_HIBRT_L     = 0x0B,
0381     MAX77836_FG_REG_CONFIG_H    = 0x0C,
0382     MAX77836_FG_REG_CONFIG_L    = 0x0D,
0383     MAX77836_FG_REG_VALRT_MIN   = 0x14,
0384     MAX77836_FG_REG_VALRT_MAX   = 0x15,
0385     MAX77836_FG_REG_CRATE_MSB   = 0x16,
0386     MAX77836_FG_REG_CRATE_LSB   = 0x17,
0387     MAX77836_FG_REG_VRESET      = 0x18,
0388     MAX77836_FG_REG_FGID        = 0x19,
0389     MAX77836_FG_REG_STATUS_H    = 0x1A,
0390     MAX77836_FG_REG_STATUS_L    = 0x1B,
0391     /*
0392      * TODO: TABLE registers
0393      * TODO: CMD register
0394      */
0395
0396     MAX77836_FG_REG_END,
0397 };
0398
0399 enum max14577_irq {
0400     /* INT1 */
0401     MAX14577_IRQ_INT1_ADC,
0402     MAX14577_IRQ_INT1_ADCLOW,
0403     MAX14577_IRQ_INT1_ADCERR,
0404     MAX77836_IRQ_INT1_ADC1K,
0405
0406     /* INT2 */
0407     MAX14577_IRQ_INT2_CHGTYP,
0408     MAX14577_IRQ_INT2_CHGDETRUN,
0409     MAX14577_IRQ_INT2_DCDTMR,
0410     MAX14577_IRQ_INT2_DBCHG,
0411     MAX14577_IRQ_INT2_VBVOLT,
0412     MAX77836_IRQ_INT2_VIDRM,
0413
0414     /* INT3 */
0415     MAX14577_IRQ_INT3_EOC,
0416     MAX14577_IRQ_INT3_CGMBC,
0417     MAX14577_IRQ_INT3_OVP,
0418     MAX14577_IRQ_INT3_MBCCHGERR,
0419
0420     /* TOPSYS_INT, only MAX77836 */
0421     MAX77836_IRQ_TOPSYS_T140C,
0422     MAX77836_IRQ_TOPSYS_T120C,
0423
0424     MAX14577_IRQ_NUM,
0425 };
0426
0427 struct max14577 {
0428     struct device *dev;
0429     struct i2c_client *i2c; /* Slave addr = 0x4A */
0430     struct i2c_client *i2c_pmic; /* Slave addr = 0x46 */
0431     enum maxim_device_type dev_type;
0432
0433     struct regmap *regmap; /* For MUIC and Charger */
0434     struct regmap *regmap_pmic;
0435
0436     struct regmap_irq_chip_data *irq_data; /* For MUIC and Charger */
0437     struct regmap_irq_chip_data *irq_data_pmic;
0438     int irq;
0439 };
0440
0441 /* MAX14577 shared regmap API function */
0442 static inline int max14577_read_reg(struct regmap *map, u8 reg, u8 *dest)
0443 {
0444     unsigned int val;
0445     int ret;
0446
0447     ret = regmap_read(map, reg, &val);
0448     *dest = val;
0449
0450     return ret;
0451 }
0452
0453 static inline int max14577_bulk_read(struct regmap *map, u8 reg, u8 *buf,
0454         int count)
0455 {
0456     return regmap_bulk_read(map, reg, buf, count);
0457 }
0458
0459 static inline int max14577_write_reg(struct regmap *map, u8 reg, u8 value)
0460 {
0461     return regmap_write(map, reg, value);
0462 }
0463
0464 static inline int max14577_bulk_write(struct regmap *map, u8 reg, u8 *buf,
0465         int count)
0466 {
0467     return regmap_bulk_write(map, reg, buf, count);
0468 }
0469
0470 static inline int max14577_update_reg(struct regmap *map, u8 reg, u8 mask,
0471         u8 val)
0472 {
0473     return regmap_update_bits(map, reg, mask, val);
0474 }
0475
0476 #endif /* __MAX14577_PRIVATE_H__ */