linux/mfd/lp3943.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * TI/National Semiconductor LP3943 Device
0004  *
0005  * Copyright 2013 Texas Instruments
0006  *
0007  * Author: Milo Kim <milo.kim@ti.com>
0008  */
0009
0010 #ifndef __MFD_LP3943_H__
0011 #define __MFD_LP3943_H__
0012
0013 #include <linux/gpio.h>
0014 #include <linux/pwm.h>
0015 #include <linux/regmap.h>
0016
0017 /* Registers */
0018 #define LP3943_REG_GPIO_A       0x00
0019 #define LP3943_REG_GPIO_B       0x01
0020 #define LP3943_REG_PRESCALE0        0x02
0021 #define LP3943_REG_PWM0         0x03
0022 #define LP3943_REG_PRESCALE1        0x04
0023 #define LP3943_REG_PWM1         0x05
0024 #define LP3943_REG_MUX0         0x06
0025 #define LP3943_REG_MUX1         0x07
0026 #define LP3943_REG_MUX2         0x08
0027 #define LP3943_REG_MUX3         0x09
0028
0029 /* Bit description for LP3943_REG_MUX0 ~ 3 */
0030 #define LP3943_GPIO_IN          0x00
0031 #define LP3943_GPIO_OUT_HIGH        0x00
0032 #define LP3943_GPIO_OUT_LOW     0x01
0033 #define LP3943_DIM_PWM0         0x02
0034 #define LP3943_DIM_PWM1         0x03
0035
0036 #define LP3943_NUM_PWMS         2
0037
0038 enum lp3943_pwm_output {
0039     LP3943_PWM_OUT0,
0040     LP3943_PWM_OUT1,
0041     LP3943_PWM_OUT2,
0042     LP3943_PWM_OUT3,
0043     LP3943_PWM_OUT4,
0044     LP3943_PWM_OUT5,
0045     LP3943_PWM_OUT6,
0046     LP3943_PWM_OUT7,
0047     LP3943_PWM_OUT8,
0048     LP3943_PWM_OUT9,
0049     LP3943_PWM_OUT10,
0050     LP3943_PWM_OUT11,
0051     LP3943_PWM_OUT12,
0052     LP3943_PWM_OUT13,
0053     LP3943_PWM_OUT14,
0054     LP3943_PWM_OUT15,
0055 };
0056
0057 /*
0058  * struct lp3943_pwm_map
0059  * @output: Output pins which are mapped to each PWM channel
0060  * @num_outputs: Number of outputs
0061  */
0062 struct lp3943_pwm_map {
0063     enum lp3943_pwm_output *output;
0064     int num_outputs;
0065 };
0066
0067 /*
0068  * struct lp3943_platform_data
0069  * @pwms: Output channel definitions for PWM channel 0 and 1
0070  */
0071 struct lp3943_platform_data {
0072     struct lp3943_pwm_map *pwms[LP3943_NUM_PWMS];
0073 };
0074
0075 /*
0076  * struct lp3943_reg_cfg
0077  * @reg: Register address
0078  * @mask: Register bit mask to be updated
0079  * @shift: Register bit shift
0080  */
0081 struct lp3943_reg_cfg {
0082     u8 reg;
0083     u8 mask;
0084     u8 shift;
0085 };
0086
0087 /*
0088  * struct lp3943
0089  * @dev: Parent device pointer
0090  * @regmap: Used for I2C communication on accessing registers
0091  * @pdata: LP3943 platform specific data
0092  * @mux_cfg: Register configuration for pin MUX
0093  * @pin_used: Bit mask for output pin used.
0094  *        This bitmask is used for pin assignment management.
0095  *        1 = pin used, 0 = available.
0096  *        Only LSB 16 bits are used, but it is unsigned long type
0097  *        for atomic bitwise operations.
0098  */
0099 struct lp3943 {
0100     struct device *dev;
0101     struct regmap *regmap;
0102     struct lp3943_platform_data *pdata;
0103     const struct lp3943_reg_cfg *mux_cfg;
0104     unsigned long pin_used;
0105 };
0106
0107 int lp3943_read_byte(struct lp3943 *lp3943, u8 reg, u8 *read);
0108 int lp3943_write_byte(struct lp3943 *lp3943, u8 reg, u8 data);
0109 int lp3943_update_bits(struct lp3943 *lp3943, u8 reg, u8 mask, u8 data);
0110 #endif