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0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Lochnagar2 register definitions
0004  *
0005  * Copyright (c) 2017-2018 Cirrus Logic, Inc. and
0006  *                         Cirrus Logic International Semiconductor Ltd.
0007  *
0008  * Author: Charles Keepax <ckeepax@opensource.cirrus.com>
0009  */
0010 
0011 #ifndef LOCHNAGAR2_REGISTERS_H
0012 #define LOCHNAGAR2_REGISTERS_H
0013 
0014 /* Register Addresses */
0015 #define LOCHNAGAR2_CDC_AIF1_CTRL                      0x000D
0016 #define LOCHNAGAR2_CDC_AIF2_CTRL                      0x000E
0017 #define LOCHNAGAR2_CDC_AIF3_CTRL                      0x000F
0018 #define LOCHNAGAR2_DSP_AIF1_CTRL                      0x0010
0019 #define LOCHNAGAR2_DSP_AIF2_CTRL                      0x0011
0020 #define LOCHNAGAR2_PSIA1_CTRL                         0x0012
0021 #define LOCHNAGAR2_PSIA2_CTRL                         0x0013
0022 #define LOCHNAGAR2_GF_AIF3_CTRL                       0x0014
0023 #define LOCHNAGAR2_GF_AIF4_CTRL                       0x0015
0024 #define LOCHNAGAR2_GF_AIF1_CTRL                       0x0016
0025 #define LOCHNAGAR2_GF_AIF2_CTRL                       0x0017
0026 #define LOCHNAGAR2_SPDIF_AIF_CTRL                     0x0018
0027 #define LOCHNAGAR2_USB_AIF1_CTRL                      0x0019
0028 #define LOCHNAGAR2_USB_AIF2_CTRL                      0x001A
0029 #define LOCHNAGAR2_ADAT_AIF_CTRL                      0x001B
0030 #define LOCHNAGAR2_CDC_MCLK1_CTRL                     0x001E
0031 #define LOCHNAGAR2_CDC_MCLK2_CTRL                     0x001F
0032 #define LOCHNAGAR2_DSP_CLKIN_CTRL                     0x0020
0033 #define LOCHNAGAR2_PSIA1_MCLK_CTRL                    0x0021
0034 #define LOCHNAGAR2_PSIA2_MCLK_CTRL                    0x0022
0035 #define LOCHNAGAR2_SPDIF_MCLK_CTRL                    0x0023
0036 #define LOCHNAGAR2_GF_CLKOUT1_CTRL                    0x0024
0037 #define LOCHNAGAR2_GF_CLKOUT2_CTRL                    0x0025
0038 #define LOCHNAGAR2_ADAT_MCLK_CTRL                     0x0026
0039 #define LOCHNAGAR2_SOUNDCARD_MCLK_CTRL                0x0027
0040 #define LOCHNAGAR2_GPIO_FPGA_GPIO1                    0x0031
0041 #define LOCHNAGAR2_GPIO_FPGA_GPIO2                    0x0032
0042 #define LOCHNAGAR2_GPIO_FPGA_GPIO3                    0x0033
0043 #define LOCHNAGAR2_GPIO_FPGA_GPIO4                    0x0034
0044 #define LOCHNAGAR2_GPIO_FPGA_GPIO5                    0x0035
0045 #define LOCHNAGAR2_GPIO_FPGA_GPIO6                    0x0036
0046 #define LOCHNAGAR2_GPIO_CDC_GPIO1                     0x0037
0047 #define LOCHNAGAR2_GPIO_CDC_GPIO2                     0x0038
0048 #define LOCHNAGAR2_GPIO_CDC_GPIO3                     0x0039
0049 #define LOCHNAGAR2_GPIO_CDC_GPIO4                     0x003A
0050 #define LOCHNAGAR2_GPIO_CDC_GPIO5                     0x003B
0051 #define LOCHNAGAR2_GPIO_CDC_GPIO6                     0x003C
0052 #define LOCHNAGAR2_GPIO_CDC_GPIO7                     0x003D
0053 #define LOCHNAGAR2_GPIO_CDC_GPIO8                     0x003E
0054 #define LOCHNAGAR2_GPIO_DSP_GPIO1                     0x003F
0055 #define LOCHNAGAR2_GPIO_DSP_GPIO2                     0x0040
0056 #define LOCHNAGAR2_GPIO_DSP_GPIO3                     0x0041
0057 #define LOCHNAGAR2_GPIO_DSP_GPIO4                     0x0042
0058 #define LOCHNAGAR2_GPIO_DSP_GPIO5                     0x0043
0059 #define LOCHNAGAR2_GPIO_DSP_GPIO6                     0x0044
0060 #define LOCHNAGAR2_GPIO_GF_GPIO2                      0x0045
0061 #define LOCHNAGAR2_GPIO_GF_GPIO3                      0x0046
0062 #define LOCHNAGAR2_GPIO_GF_GPIO7                      0x0047
0063 #define LOCHNAGAR2_GPIO_CDC_AIF1_BCLK                 0x0048
0064 #define LOCHNAGAR2_GPIO_CDC_AIF1_RXDAT                0x0049
0065 #define LOCHNAGAR2_GPIO_CDC_AIF1_LRCLK                0x004A
0066 #define LOCHNAGAR2_GPIO_CDC_AIF1_TXDAT                0x004B
0067 #define LOCHNAGAR2_GPIO_CDC_AIF2_BCLK                 0x004C
0068 #define LOCHNAGAR2_GPIO_CDC_AIF2_RXDAT                0x004D
0069 #define LOCHNAGAR2_GPIO_CDC_AIF2_LRCLK                0x004E
0070 #define LOCHNAGAR2_GPIO_CDC_AIF2_TXDAT                0x004F
0071 #define LOCHNAGAR2_GPIO_CDC_AIF3_BCLK                 0x0050
0072 #define LOCHNAGAR2_GPIO_CDC_AIF3_RXDAT                0x0051
0073 #define LOCHNAGAR2_GPIO_CDC_AIF3_LRCLK                0x0052
0074 #define LOCHNAGAR2_GPIO_CDC_AIF3_TXDAT                0x0053
0075 #define LOCHNAGAR2_GPIO_DSP_AIF1_BCLK                 0x0054
0076 #define LOCHNAGAR2_GPIO_DSP_AIF1_RXDAT                0x0055
0077 #define LOCHNAGAR2_GPIO_DSP_AIF1_LRCLK                0x0056
0078 #define LOCHNAGAR2_GPIO_DSP_AIF1_TXDAT                0x0057
0079 #define LOCHNAGAR2_GPIO_DSP_AIF2_BCLK                 0x0058
0080 #define LOCHNAGAR2_GPIO_DSP_AIF2_RXDAT                0x0059
0081 #define LOCHNAGAR2_GPIO_DSP_AIF2_LRCLK                0x005A
0082 #define LOCHNAGAR2_GPIO_DSP_AIF2_TXDAT                0x005B
0083 #define LOCHNAGAR2_GPIO_PSIA1_BCLK                    0x005C
0084 #define LOCHNAGAR2_GPIO_PSIA1_RXDAT                   0x005D
0085 #define LOCHNAGAR2_GPIO_PSIA1_LRCLK                   0x005E
0086 #define LOCHNAGAR2_GPIO_PSIA1_TXDAT                   0x005F
0087 #define LOCHNAGAR2_GPIO_PSIA2_BCLK                    0x0060
0088 #define LOCHNAGAR2_GPIO_PSIA2_RXDAT                   0x0061
0089 #define LOCHNAGAR2_GPIO_PSIA2_LRCLK                   0x0062
0090 #define LOCHNAGAR2_GPIO_PSIA2_TXDAT                   0x0063
0091 #define LOCHNAGAR2_GPIO_GF_AIF3_BCLK                  0x0064
0092 #define LOCHNAGAR2_GPIO_GF_AIF3_RXDAT                 0x0065
0093 #define LOCHNAGAR2_GPIO_GF_AIF3_LRCLK                 0x0066
0094 #define LOCHNAGAR2_GPIO_GF_AIF3_TXDAT                 0x0067
0095 #define LOCHNAGAR2_GPIO_GF_AIF4_BCLK                  0x0068
0096 #define LOCHNAGAR2_GPIO_GF_AIF4_RXDAT                 0x0069
0097 #define LOCHNAGAR2_GPIO_GF_AIF4_LRCLK                 0x006A
0098 #define LOCHNAGAR2_GPIO_GF_AIF4_TXDAT                 0x006B
0099 #define LOCHNAGAR2_GPIO_GF_AIF1_BCLK                  0x006C
0100 #define LOCHNAGAR2_GPIO_GF_AIF1_RXDAT                 0x006D
0101 #define LOCHNAGAR2_GPIO_GF_AIF1_LRCLK                 0x006E
0102 #define LOCHNAGAR2_GPIO_GF_AIF1_TXDAT                 0x006F
0103 #define LOCHNAGAR2_GPIO_GF_AIF2_BCLK                  0x0070
0104 #define LOCHNAGAR2_GPIO_GF_AIF2_RXDAT                 0x0071
0105 #define LOCHNAGAR2_GPIO_GF_AIF2_LRCLK                 0x0072
0106 #define LOCHNAGAR2_GPIO_GF_AIF2_TXDAT                 0x0073
0107 #define LOCHNAGAR2_GPIO_DSP_UART1_RX                  0x0074
0108 #define LOCHNAGAR2_GPIO_DSP_UART1_TX                  0x0075
0109 #define LOCHNAGAR2_GPIO_DSP_UART2_RX                  0x0076
0110 #define LOCHNAGAR2_GPIO_DSP_UART2_TX                  0x0077
0111 #define LOCHNAGAR2_GPIO_GF_UART2_RX                   0x0078
0112 #define LOCHNAGAR2_GPIO_GF_UART2_TX                   0x0079
0113 #define LOCHNAGAR2_GPIO_USB_UART_RX                   0x007A
0114 #define LOCHNAGAR2_GPIO_CDC_PDMCLK1                   0x007C
0115 #define LOCHNAGAR2_GPIO_CDC_PDMDAT1                   0x007D
0116 #define LOCHNAGAR2_GPIO_CDC_PDMCLK2                   0x007E
0117 #define LOCHNAGAR2_GPIO_CDC_PDMDAT2                   0x007F
0118 #define LOCHNAGAR2_GPIO_CDC_DMICCLK1                  0x0080
0119 #define LOCHNAGAR2_GPIO_CDC_DMICDAT1                  0x0081
0120 #define LOCHNAGAR2_GPIO_CDC_DMICCLK2                  0x0082
0121 #define LOCHNAGAR2_GPIO_CDC_DMICDAT2                  0x0083
0122 #define LOCHNAGAR2_GPIO_CDC_DMICCLK3                  0x0084
0123 #define LOCHNAGAR2_GPIO_CDC_DMICDAT3                  0x0085
0124 #define LOCHNAGAR2_GPIO_CDC_DMICCLK4                  0x0086
0125 #define LOCHNAGAR2_GPIO_CDC_DMICDAT4                  0x0087
0126 #define LOCHNAGAR2_GPIO_DSP_DMICCLK1                  0x0088
0127 #define LOCHNAGAR2_GPIO_DSP_DMICDAT1                  0x0089
0128 #define LOCHNAGAR2_GPIO_DSP_DMICCLK2                  0x008A
0129 #define LOCHNAGAR2_GPIO_DSP_DMICDAT2                  0x008B
0130 #define LOCHNAGAR2_GPIO_I2C2_SCL                      0x008C
0131 #define LOCHNAGAR2_GPIO_I2C2_SDA                      0x008D
0132 #define LOCHNAGAR2_GPIO_I2C3_SCL                      0x008E
0133 #define LOCHNAGAR2_GPIO_I2C3_SDA                      0x008F
0134 #define LOCHNAGAR2_GPIO_I2C4_SCL                      0x0090
0135 #define LOCHNAGAR2_GPIO_I2C4_SDA                      0x0091
0136 #define LOCHNAGAR2_GPIO_DSP_STANDBY                   0x0092
0137 #define LOCHNAGAR2_GPIO_CDC_MCLK1                     0x0093
0138 #define LOCHNAGAR2_GPIO_CDC_MCLK2                     0x0094
0139 #define LOCHNAGAR2_GPIO_DSP_CLKIN                     0x0095
0140 #define LOCHNAGAR2_GPIO_PSIA1_MCLK                    0x0096
0141 #define LOCHNAGAR2_GPIO_PSIA2_MCLK                    0x0097
0142 #define LOCHNAGAR2_GPIO_GF_GPIO1                      0x0098
0143 #define LOCHNAGAR2_GPIO_GF_GPIO5                      0x0099
0144 #define LOCHNAGAR2_GPIO_DSP_GPIO20                    0x009A
0145 #define LOCHNAGAR2_GPIO_CHANNEL1                      0x00B9
0146 #define LOCHNAGAR2_GPIO_CHANNEL2                      0x00BA
0147 #define LOCHNAGAR2_GPIO_CHANNEL3                      0x00BB
0148 #define LOCHNAGAR2_GPIO_CHANNEL4                      0x00BC
0149 #define LOCHNAGAR2_GPIO_CHANNEL5                      0x00BD
0150 #define LOCHNAGAR2_GPIO_CHANNEL6                      0x00BE
0151 #define LOCHNAGAR2_GPIO_CHANNEL7                      0x00BF
0152 #define LOCHNAGAR2_GPIO_CHANNEL8                      0x00C0
0153 #define LOCHNAGAR2_GPIO_CHANNEL9                      0x00C1
0154 #define LOCHNAGAR2_GPIO_CHANNEL10                     0x00C2
0155 #define LOCHNAGAR2_GPIO_CHANNEL11                     0x00C3
0156 #define LOCHNAGAR2_GPIO_CHANNEL12                     0x00C4
0157 #define LOCHNAGAR2_GPIO_CHANNEL13                     0x00C5
0158 #define LOCHNAGAR2_GPIO_CHANNEL14                     0x00C6
0159 #define LOCHNAGAR2_GPIO_CHANNEL15                     0x00C7
0160 #define LOCHNAGAR2_GPIO_CHANNEL16                     0x00C8
0161 #define LOCHNAGAR2_MINICARD_RESETS                    0x00DF
0162 #define LOCHNAGAR2_ANALOGUE_PATH_CTRL1                0x00E3
0163 #define LOCHNAGAR2_ANALOGUE_PATH_CTRL2                0x00E4
0164 #define LOCHNAGAR2_COMMS_CTRL4                        0x00F0
0165 #define LOCHNAGAR2_SPDIF_CTRL                         0x00FE
0166 #define LOCHNAGAR2_IMON_CTRL1                         0x0108
0167 #define LOCHNAGAR2_IMON_CTRL2                         0x0109
0168 #define LOCHNAGAR2_IMON_CTRL3                         0x010A
0169 #define LOCHNAGAR2_IMON_CTRL4                         0x010B
0170 #define LOCHNAGAR2_IMON_DATA1                         0x010C
0171 #define LOCHNAGAR2_IMON_DATA2                         0x010D
0172 #define LOCHNAGAR2_POWER_CTRL                         0x0116
0173 #define LOCHNAGAR2_MICVDD_CTRL1                       0x0119
0174 #define LOCHNAGAR2_MICVDD_CTRL2                       0x011B
0175 #define LOCHNAGAR2_VDDCORE_CDC_CTRL1                  0x011E
0176 #define LOCHNAGAR2_VDDCORE_CDC_CTRL2                  0x0120
0177 #define LOCHNAGAR2_SOUNDCARD_AIF_CTRL                 0x0180
0178 
0179 /* (0x000D-0x001B, 0x0180)  CDC_AIF1_CTRL - SOUNCARD_AIF_CTRL */
0180 #define LOCHNAGAR2_AIF_ENA_MASK                       0x8000
0181 #define LOCHNAGAR2_AIF_ENA_SHIFT                          15
0182 #define LOCHNAGAR2_AIF_LRCLK_DIR_MASK                 0x4000
0183 #define LOCHNAGAR2_AIF_LRCLK_DIR_SHIFT                    14
0184 #define LOCHNAGAR2_AIF_BCLK_DIR_MASK                  0x2000
0185 #define LOCHNAGAR2_AIF_BCLK_DIR_SHIFT                     13
0186 #define LOCHNAGAR2_AIF_SRC_MASK                       0x00FF
0187 #define LOCHNAGAR2_AIF_SRC_SHIFT                           0
0188 
0189 /* (0x001E - 0x0027)  CDC_MCLK1_CTRL - SOUNDCARD_MCLK_CTRL */
0190 #define LOCHNAGAR2_CLK_ENA_MASK                       0x8000
0191 #define LOCHNAGAR2_CLK_ENA_SHIFT                          15
0192 #define LOCHNAGAR2_CLK_SRC_MASK                       0x00FF
0193 #define LOCHNAGAR2_CLK_SRC_SHIFT                           0
0194 
0195 /* (0x0031 - 0x009A)  GPIO_FPGA_GPIO1 - GPIO_DSP_GPIO20 */
0196 #define LOCHNAGAR2_GPIO_SRC_MASK                      0x00FF
0197 #define LOCHNAGAR2_GPIO_SRC_SHIFT                          0
0198 
0199 /* (0x00B9 - 0x00C8)  GPIO_CHANNEL1 - GPIO_CHANNEL16 */
0200 #define LOCHNAGAR2_GPIO_CHANNEL_STS_MASK              0x8000
0201 #define LOCHNAGAR2_GPIO_CHANNEL_STS_SHIFT                 15
0202 #define LOCHNAGAR2_GPIO_CHANNEL_SRC_MASK              0x00FF
0203 #define LOCHNAGAR2_GPIO_CHANNEL_SRC_SHIFT                  0
0204 
0205 /* (0x00DF)  MINICARD_RESETS */
0206 #define LOCHNAGAR2_DSP_RESET_MASK                     0x0002
0207 #define LOCHNAGAR2_DSP_RESET_SHIFT                         1
0208 #define LOCHNAGAR2_CDC_RESET_MASK                     0x0001
0209 #define LOCHNAGAR2_CDC_RESET_SHIFT                         0
0210 
0211 /* (0x00E3)  ANALOGUE_PATH_CTRL1 */
0212 #define LOCHNAGAR2_ANALOGUE_PATH_UPDATE_MASK          0x8000
0213 #define LOCHNAGAR2_ANALOGUE_PATH_UPDATE_SHIFT             15
0214 #define LOCHNAGAR2_ANALOGUE_PATH_UPDATE_STS_MASK      0x4000
0215 #define LOCHNAGAR2_ANALOGUE_PATH_UPDATE_STS_SHIFT         14
0216 
0217 /* (0x00E4)  ANALOGUE_PATH_CTRL2 */
0218 #define LOCHNAGAR2_P2_INPUT_BIAS_ENA_MASK             0x0080
0219 #define LOCHNAGAR2_P2_INPUT_BIAS_ENA_SHIFT                 7
0220 #define LOCHNAGAR2_P1_INPUT_BIAS_ENA_MASK             0x0040
0221 #define LOCHNAGAR2_P1_INPUT_BIAS_ENA_SHIFT                 6
0222 #define LOCHNAGAR2_P2_MICBIAS_SRC_MASK                0x0038
0223 #define LOCHNAGAR2_P2_MICBIAS_SRC_SHIFT                    3
0224 #define LOCHNAGAR2_P1_MICBIAS_SRC_MASK                0x0007
0225 #define LOCHNAGAR2_P1_MICBIAS_SRC_SHIFT                    0
0226 
0227 /* (0x00F0)  COMMS_CTRL4 */
0228 #define LOCHNAGAR2_CDC_CIF1MODE_MASK                  0x0001
0229 #define LOCHNAGAR2_CDC_CIF1MODE_SHIFT                      0
0230 
0231 /* (0x00FE)  SPDIF_CTRL */
0232 #define LOCHNAGAR2_SPDIF_HWMODE_MASK                  0x0008
0233 #define LOCHNAGAR2_SPDIF_HWMODE_SHIFT                      3
0234 #define LOCHNAGAR2_SPDIF_RESET_MASK                   0x0001
0235 #define LOCHNAGAR2_SPDIF_RESET_SHIFT                       0
0236 
0237 /* (0x0108)  IMON_CTRL1 */
0238 #define LOCHNAGAR2_IMON_ENA_MASK                      0x8000
0239 #define LOCHNAGAR2_IMON_ENA_SHIFT                         15
0240 #define LOCHNAGAR2_IMON_MEASURED_CHANNELS_MASK        0x03FC
0241 #define LOCHNAGAR2_IMON_MEASURED_CHANNELS_SHIFT            2
0242 #define LOCHNAGAR2_IMON_MODE_SEL_MASK                 0x0003
0243 #define LOCHNAGAR2_IMON_MODE_SEL_SHIFT                     0
0244 
0245 /* (0x0109)  IMON_CTRL2 */
0246 #define LOCHNAGAR2_IMON_FSR_MASK                      0x03FF
0247 #define LOCHNAGAR2_IMON_FSR_SHIFT                          0
0248 
0249 /* (0x010A)  IMON_CTRL3 */
0250 #define LOCHNAGAR2_IMON_DONE_MASK                     0x0004
0251 #define LOCHNAGAR2_IMON_DONE_SHIFT                         2
0252 #define LOCHNAGAR2_IMON_CONFIGURE_MASK                0x0002
0253 #define LOCHNAGAR2_IMON_CONFIGURE_SHIFT                    1
0254 #define LOCHNAGAR2_IMON_MEASURE_MASK                  0x0001
0255 #define LOCHNAGAR2_IMON_MEASURE_SHIFT                      0
0256 
0257 /* (0x010B)  IMON_CTRL4 */
0258 #define LOCHNAGAR2_IMON_DATA_REQ_MASK                 0x0080
0259 #define LOCHNAGAR2_IMON_DATA_REQ_SHIFT                     7
0260 #define LOCHNAGAR2_IMON_CH_SEL_MASK                   0x0070
0261 #define LOCHNAGAR2_IMON_CH_SEL_SHIFT                       4
0262 #define LOCHNAGAR2_IMON_DATA_RDY_MASK                 0x0008
0263 #define LOCHNAGAR2_IMON_DATA_RDY_SHIFT                     3
0264 #define LOCHNAGAR2_IMON_CH_SRC_MASK                   0x0007
0265 #define LOCHNAGAR2_IMON_CH_SRC_SHIFT                       0
0266 
0267 /* (0x010C, 0x010D)  IMON_DATA1, IMON_DATA2 */
0268 #define LOCHNAGAR2_IMON_DATA_MASK                     0xFFFF
0269 #define LOCHNAGAR2_IMON_DATA_SHIFT                         0
0270 
0271 /* (0x0116)  POWER_CTRL */
0272 #define LOCHNAGAR2_PWR_ENA_MASK                       0x0001
0273 #define LOCHNAGAR2_PWR_ENA_SHIFT                           0
0274 
0275 /* (0x0119)  MICVDD_CTRL1 */
0276 #define LOCHNAGAR2_MICVDD_REG_ENA_MASK                0x8000
0277 #define LOCHNAGAR2_MICVDD_REG_ENA_SHIFT                   15
0278 
0279 /* (0x011B)  MICVDD_CTRL2 */
0280 #define LOCHNAGAR2_MICVDD_VSEL_MASK                   0x001F
0281 #define LOCHNAGAR2_MICVDD_VSEL_SHIFT                       0
0282 
0283 /* (0x011E)  VDDCORE_CDC_CTRL1 */
0284 #define LOCHNAGAR2_VDDCORE_CDC_REG_ENA_MASK           0x8000
0285 #define LOCHNAGAR2_VDDCORE_CDC_REG_ENA_SHIFT              15
0286 
0287 /* (0x0120)  VDDCORE_CDC_CTRL2 */
0288 #define LOCHNAGAR2_VDDCORE_CDC_VSEL_MASK              0x007F
0289 #define LOCHNAGAR2_VDDCORE_CDC_VSEL_SHIFT                  0
0290 
0291 #endif
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