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0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Lochnagar1 register definitions
0004  *
0005  * Copyright (c) 2017-2018 Cirrus Logic, Inc. and
0006  *                         Cirrus Logic International Semiconductor Ltd.
0007  *
0008  * Author: Charles Keepax <ckeepax@opensource.cirrus.com>
0009  */
0010 
0011 #ifndef LOCHNAGAR1_REGISTERS_H
0012 #define LOCHNAGAR1_REGISTERS_H
0013 
0014 /* Register Addresses */
0015 #define LOCHNAGAR1_CDC_AIF1_SEL                       0x0008
0016 #define LOCHNAGAR1_CDC_AIF2_SEL                       0x0009
0017 #define LOCHNAGAR1_CDC_AIF3_SEL                       0x000A
0018 #define LOCHNAGAR1_CDC_MCLK1_SEL                      0x000B
0019 #define LOCHNAGAR1_CDC_MCLK2_SEL                      0x000C
0020 #define LOCHNAGAR1_CDC_AIF_CTRL1                      0x000D
0021 #define LOCHNAGAR1_CDC_AIF_CTRL2                      0x000E
0022 #define LOCHNAGAR1_EXT_AIF_CTRL                       0x000F
0023 #define LOCHNAGAR1_DSP_AIF1_SEL                       0x0010
0024 #define LOCHNAGAR1_DSP_AIF2_SEL                       0x0011
0025 #define LOCHNAGAR1_DSP_CLKIN_SEL                      0x0012
0026 #define LOCHNAGAR1_DSP_AIF                            0x0013
0027 #define LOCHNAGAR1_GF_AIF1                            0x0014
0028 #define LOCHNAGAR1_GF_AIF2                            0x0015
0029 #define LOCHNAGAR1_PSIA_AIF                           0x0016
0030 #define LOCHNAGAR1_PSIA1_SEL                          0x0017
0031 #define LOCHNAGAR1_PSIA2_SEL                          0x0018
0032 #define LOCHNAGAR1_SPDIF_AIF_SEL                      0x0019
0033 #define LOCHNAGAR1_GF_AIF3_SEL                        0x001C
0034 #define LOCHNAGAR1_GF_AIF4_SEL                        0x001D
0035 #define LOCHNAGAR1_GF_CLKOUT1_SEL                     0x001E
0036 #define LOCHNAGAR1_GF_AIF1_SEL                        0x001F
0037 #define LOCHNAGAR1_GF_AIF2_SEL                        0x0020
0038 #define LOCHNAGAR1_GF_GPIO2                           0x0026
0039 #define LOCHNAGAR1_GF_GPIO3                           0x0027
0040 #define LOCHNAGAR1_GF_GPIO7                           0x0028
0041 #define LOCHNAGAR1_RST                                0x0029
0042 #define LOCHNAGAR1_LED1                               0x002A
0043 #define LOCHNAGAR1_LED2                               0x002B
0044 #define LOCHNAGAR1_I2C_CTRL                           0x0046
0045 
0046 /*
0047  * (0x0008 - 0x000C, 0x0010 - 0x0012, 0x0017 - 0x0020)
0048  * CDC_AIF1_SEL - GF_AIF2_SEL
0049  */
0050 #define LOCHNAGAR1_SRC_MASK                             0xFF
0051 #define LOCHNAGAR1_SRC_SHIFT                               0
0052 
0053 /* (0x000D)  CDC_AIF_CTRL1 */
0054 #define LOCHNAGAR1_CDC_AIF2_LRCLK_DIR_MASK              0x40
0055 #define LOCHNAGAR1_CDC_AIF2_LRCLK_DIR_SHIFT                6
0056 #define LOCHNAGAR1_CDC_AIF2_BCLK_DIR_MASK               0x20
0057 #define LOCHNAGAR1_CDC_AIF2_BCLK_DIR_SHIFT                 5
0058 #define LOCHNAGAR1_CDC_AIF2_ENA_MASK                    0x10
0059 #define LOCHNAGAR1_CDC_AIF2_ENA_SHIFT                      4
0060 #define LOCHNAGAR1_CDC_AIF1_LRCLK_DIR_MASK              0x04
0061 #define LOCHNAGAR1_CDC_AIF1_LRCLK_DIR_SHIFT                2
0062 #define LOCHNAGAR1_CDC_AIF1_BCLK_DIR_MASK               0x02
0063 #define LOCHNAGAR1_CDC_AIF1_BCLK_DIR_SHIFT                 1
0064 #define LOCHNAGAR1_CDC_AIF1_ENA_MASK                    0x01
0065 #define LOCHNAGAR1_CDC_AIF1_ENA_SHIFT                      0
0066 
0067 /* (0x000E)  CDC_AIF_CTRL2 */
0068 #define LOCHNAGAR1_CDC_AIF3_LRCLK_DIR_MASK              0x40
0069 #define LOCHNAGAR1_CDC_AIF3_LRCLK_DIR_SHIFT                6
0070 #define LOCHNAGAR1_CDC_AIF3_BCLK_DIR_MASK               0x20
0071 #define LOCHNAGAR1_CDC_AIF3_BCLK_DIR_SHIFT                 5
0072 #define LOCHNAGAR1_CDC_AIF3_ENA_MASK                    0x10
0073 #define LOCHNAGAR1_CDC_AIF3_ENA_SHIFT                      4
0074 #define LOCHNAGAR1_CDC_MCLK1_ENA_MASK                   0x02
0075 #define LOCHNAGAR1_CDC_MCLK1_ENA_SHIFT                     1
0076 #define LOCHNAGAR1_CDC_MCLK2_ENA_MASK                   0x01
0077 #define LOCHNAGAR1_CDC_MCLK2_ENA_SHIFT                     0
0078 
0079 /* (0x000F)  EXT_AIF_CTRL */
0080 #define LOCHNAGAR1_SPDIF_AIF_LRCLK_DIR_MASK             0x20
0081 #define LOCHNAGAR1_SPDIF_AIF_LRCLK_DIR_SHIFT               5
0082 #define LOCHNAGAR1_SPDIF_AIF_BCLK_DIR_MASK              0x10
0083 #define LOCHNAGAR1_SPDIF_AIF_BCLK_DIR_SHIFT                4
0084 #define LOCHNAGAR1_SPDIF_AIF_ENA_MASK                   0x08
0085 #define LOCHNAGAR1_SPDIF_AIF_ENA_SHIFT                     3
0086 
0087 /* (0x0013)  DSP_AIF */
0088 #define LOCHNAGAR1_DSP_AIF2_LRCLK_DIR_MASK              0x40
0089 #define LOCHNAGAR1_DSP_AIF2_LRCLK_DIR_SHIFT                6
0090 #define LOCHNAGAR1_DSP_AIF2_BCLK_DIR_MASK               0x20
0091 #define LOCHNAGAR1_DSP_AIF2_BCLK_DIR_SHIFT                 5
0092 #define LOCHNAGAR1_DSP_AIF2_ENA_MASK                    0x10
0093 #define LOCHNAGAR1_DSP_AIF2_ENA_SHIFT                      4
0094 #define LOCHNAGAR1_DSP_CLKIN_ENA_MASK                   0x08
0095 #define LOCHNAGAR1_DSP_CLKIN_ENA_SHIFT                     3
0096 #define LOCHNAGAR1_DSP_AIF1_LRCLK_DIR_MASK              0x04
0097 #define LOCHNAGAR1_DSP_AIF1_LRCLK_DIR_SHIFT                2
0098 #define LOCHNAGAR1_DSP_AIF1_BCLK_DIR_MASK               0x02
0099 #define LOCHNAGAR1_DSP_AIF1_BCLK_DIR_SHIFT                 1
0100 #define LOCHNAGAR1_DSP_AIF1_ENA_MASK                    0x01
0101 #define LOCHNAGAR1_DSP_AIF1_ENA_SHIFT                      0
0102 
0103 /* (0x0014)  GF_AIF1 */
0104 #define LOCHNAGAR1_GF_CLKOUT1_ENA_MASK                  0x40
0105 #define LOCHNAGAR1_GF_CLKOUT1_ENA_SHIFT                    6
0106 #define LOCHNAGAR1_GF_AIF3_LRCLK_DIR_MASK               0x20
0107 #define LOCHNAGAR1_GF_AIF3_LRCLK_DIR_SHIFT                 5
0108 #define LOCHNAGAR1_GF_AIF3_BCLK_DIR_MASK                0x10
0109 #define LOCHNAGAR1_GF_AIF3_BCLK_DIR_SHIFT                  4
0110 #define LOCHNAGAR1_GF_AIF3_ENA_MASK                     0x08
0111 #define LOCHNAGAR1_GF_AIF3_ENA_SHIFT                       3
0112 #define LOCHNAGAR1_GF_AIF1_LRCLK_DIR_MASK               0x04
0113 #define LOCHNAGAR1_GF_AIF1_LRCLK_DIR_SHIFT                 2
0114 #define LOCHNAGAR1_GF_AIF1_BCLK_DIR_MASK                0x02
0115 #define LOCHNAGAR1_GF_AIF1_BCLK_DIR_SHIFT                  1
0116 #define LOCHNAGAR1_GF_AIF1_ENA_MASK                     0x01
0117 #define LOCHNAGAR1_GF_AIF1_ENA_SHIFT                       0
0118 
0119 /* (0x0015)  GF_AIF2 */
0120 #define LOCHNAGAR1_GF_AIF4_LRCLK_DIR_MASK               0x20
0121 #define LOCHNAGAR1_GF_AIF4_LRCLK_DIR_SHIFT                 5
0122 #define LOCHNAGAR1_GF_AIF4_BCLK_DIR_MASK                0x10
0123 #define LOCHNAGAR1_GF_AIF4_BCLK_DIR_SHIFT                  4
0124 #define LOCHNAGAR1_GF_AIF4_ENA_MASK                     0x08
0125 #define LOCHNAGAR1_GF_AIF4_ENA_SHIFT                       3
0126 #define LOCHNAGAR1_GF_AIF2_LRCLK_DIR_MASK               0x04
0127 #define LOCHNAGAR1_GF_AIF2_LRCLK_DIR_SHIFT                 2
0128 #define LOCHNAGAR1_GF_AIF2_BCLK_DIR_MASK                0x02
0129 #define LOCHNAGAR1_GF_AIF2_BCLK_DIR_SHIFT                  1
0130 #define LOCHNAGAR1_GF_AIF2_ENA_MASK                     0x01
0131 #define LOCHNAGAR1_GF_AIF2_ENA_SHIFT                       0
0132 
0133 /* (0x0016)  PSIA_AIF */
0134 #define LOCHNAGAR1_PSIA2_LRCLK_DIR_MASK                 0x40
0135 #define LOCHNAGAR1_PSIA2_LRCLK_DIR_SHIFT                   6
0136 #define LOCHNAGAR1_PSIA2_BCLK_DIR_MASK                  0x20
0137 #define LOCHNAGAR1_PSIA2_BCLK_DIR_SHIFT                    5
0138 #define LOCHNAGAR1_PSIA2_ENA_MASK                       0x10
0139 #define LOCHNAGAR1_PSIA2_ENA_SHIFT                         4
0140 #define LOCHNAGAR1_PSIA1_LRCLK_DIR_MASK                 0x04
0141 #define LOCHNAGAR1_PSIA1_LRCLK_DIR_SHIFT                   2
0142 #define LOCHNAGAR1_PSIA1_BCLK_DIR_MASK                  0x02
0143 #define LOCHNAGAR1_PSIA1_BCLK_DIR_SHIFT                    1
0144 #define LOCHNAGAR1_PSIA1_ENA_MASK                       0x01
0145 #define LOCHNAGAR1_PSIA1_ENA_SHIFT                         0
0146 
0147 /* (0x0029)  RST */
0148 #define LOCHNAGAR1_DSP_RESET_MASK                       0x02
0149 #define LOCHNAGAR1_DSP_RESET_SHIFT                         1
0150 #define LOCHNAGAR1_CDC_RESET_MASK                       0x01
0151 #define LOCHNAGAR1_CDC_RESET_SHIFT                         0
0152 
0153 /* (0x0046)  I2C_CTRL */
0154 #define LOCHNAGAR1_CDC_CIF_MODE_MASK                    0x01
0155 #define LOCHNAGAR1_CDC_CIF_MODE_SHIFT                      0
0156 
0157 #endif
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