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0008 #ifndef __LINUX_MFD_IQS62X_H
0009 #define __LINUX_MFD_IQS62X_H
0010
0011 #define IQS620_PROD_NUM 0x41
0012 #define IQS621_PROD_NUM 0x46
0013 #define IQS622_PROD_NUM 0x42
0014 #define IQS624_PROD_NUM 0x43
0015 #define IQS625_PROD_NUM 0x4E
0016
0017 #define IQS620_HW_NUM_V0 0x82
0018 #define IQS620_HW_NUM_V1 IQS620_HW_NUM_V0
0019 #define IQS620_HW_NUM_V2 IQS620_HW_NUM_V0
0020 #define IQS620_HW_NUM_V3 0x92
0021
0022 #define IQS621_ALS_FLAGS 0x16
0023 #define IQS622_ALS_FLAGS 0x14
0024
0025 #define IQS624_HALL_UI 0x70
0026 #define IQS624_HALL_UI_WHL_EVENT BIT(4)
0027 #define IQS624_HALL_UI_INT_EVENT BIT(3)
0028 #define IQS624_HALL_UI_AUTO_CAL BIT(2)
0029
0030 #define IQS624_INTERVAL_DIV 0x7D
0031
0032 #define IQS620_GLBL_EVENT_MASK 0xD7
0033 #define IQS620_GLBL_EVENT_MASK_PMU BIT(6)
0034
0035 #define IQS62X_NUM_KEYS 16
0036 #define IQS62X_NUM_EVENTS (IQS62X_NUM_KEYS + 6)
0037
0038 #define IQS62X_EVENT_SIZE 10
0039
0040 enum iqs62x_ui_sel {
0041 IQS62X_UI_PROX,
0042 IQS62X_UI_SAR1,
0043 };
0044
0045 enum iqs62x_event_reg {
0046 IQS62X_EVENT_NONE,
0047 IQS62X_EVENT_SYS,
0048 IQS62X_EVENT_PROX,
0049 IQS62X_EVENT_HYST,
0050 IQS62X_EVENT_HALL,
0051 IQS62X_EVENT_ALS,
0052 IQS62X_EVENT_IR,
0053 IQS62X_EVENT_WHEEL,
0054 IQS62X_EVENT_INTER,
0055 IQS62X_EVENT_UI_LO,
0056 IQS62X_EVENT_UI_HI,
0057 };
0058
0059 enum iqs62x_event_flag {
0060
0061 IQS62X_EVENT_PROX_CH0_T,
0062 IQS62X_EVENT_PROX_CH0_P,
0063 IQS62X_EVENT_PROX_CH1_T,
0064 IQS62X_EVENT_PROX_CH1_P,
0065 IQS62X_EVENT_PROX_CH2_T,
0066 IQS62X_EVENT_PROX_CH2_P,
0067 IQS62X_EVENT_HYST_POS_T,
0068 IQS62X_EVENT_HYST_POS_P,
0069 IQS62X_EVENT_HYST_NEG_T,
0070 IQS62X_EVENT_HYST_NEG_P,
0071 IQS62X_EVENT_SAR1_ACT,
0072 IQS62X_EVENT_SAR1_QRD,
0073 IQS62X_EVENT_SAR1_MOVE,
0074 IQS62X_EVENT_SAR1_HALT,
0075 IQS62X_EVENT_WHEEL_UP,
0076 IQS62X_EVENT_WHEEL_DN,
0077
0078
0079 IQS62X_EVENT_HALL_N_T,
0080 IQS62X_EVENT_HALL_N_P,
0081 IQS62X_EVENT_HALL_S_T,
0082 IQS62X_EVENT_HALL_S_P,
0083
0084
0085 IQS62X_EVENT_SYS_RESET,
0086 IQS62X_EVENT_SYS_ATI,
0087 };
0088
0089 struct iqs62x_event_data {
0090 u16 ui_data;
0091 u8 als_flags;
0092 u8 ir_flags;
0093 u8 interval;
0094 };
0095
0096 struct iqs62x_event_desc {
0097 enum iqs62x_event_reg reg;
0098 u8 mask;
0099 u8 val;
0100 };
0101
0102 struct iqs62x_dev_desc {
0103 const char *dev_name;
0104 const struct mfd_cell *sub_devs;
0105 int num_sub_devs;
0106 u8 prod_num;
0107 u8 sw_num;
0108 const u8 *cal_regs;
0109 int num_cal_regs;
0110 u8 prox_mask;
0111 u8 sar_mask;
0112 u8 hall_mask;
0113 u8 hyst_mask;
0114 u8 temp_mask;
0115 u8 als_mask;
0116 u8 ir_mask;
0117 u8 prox_settings;
0118 u8 als_flags;
0119 u8 hall_flags;
0120 u8 hyst_shift;
0121 u8 interval;
0122 u8 interval_div;
0123 const char *fw_name;
0124 const enum iqs62x_event_reg (*event_regs)[IQS62X_EVENT_SIZE];
0125 };
0126
0127 struct iqs62x_core {
0128 const struct iqs62x_dev_desc *dev_desc;
0129 struct i2c_client *client;
0130 struct regmap *regmap;
0131 struct blocking_notifier_head nh;
0132 struct list_head fw_blk_head;
0133 struct completion ati_done;
0134 struct completion fw_done;
0135 enum iqs62x_ui_sel ui_sel;
0136 unsigned long event_cache;
0137 u8 sw_num;
0138 u8 hw_num;
0139 };
0140
0141 extern const struct iqs62x_event_desc iqs62x_events[IQS62X_NUM_EVENTS];
0142
0143 #endif