linux/mfd/intel_pmc_bxt.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef MFD_INTEL_PMC_BXT_H
0003 #define MFD_INTEL_PMC_BXT_H
0004
0005 /* GCR reg offsets from GCR base */
0006 #define PMC_GCR_PMC_CFG_REG     0x08
0007 #define PMC_GCR_TELEM_DEEP_S0IX_REG 0x78
0008 #define PMC_GCR_TELEM_SHLW_S0IX_REG 0x80
0009
0010 /* PMC_CFG_REG bit masks */
0011 #define PMC_CFG_NO_REBOOT_EN        BIT(4)
0012
0013 /**
0014  * struct intel_pmc_dev - Intel PMC device structure
0015  * @dev: Pointer to the parent PMC device
0016  * @scu: Pointer to the SCU IPC device data structure
0017  * @gcr_mem_base: Virtual base address of GCR (Global Configuration Registers)
0018  * @gcr_lock: Lock used to serialize access to GCR registers
0019  * @telem_base: Pointer to telemetry SSRAM base resource or %NULL if not
0020  *      available
0021  */
0022 struct intel_pmc_dev {
0023     struct device *dev;
0024     struct intel_scu_ipc_dev *scu;
0025     void __iomem *gcr_mem_base;
0026     spinlock_t gcr_lock;
0027     struct resource *telem_base;
0028 };
0029
0030 #if IS_ENABLED(CONFIG_MFD_INTEL_PMC_BXT)
0031 int intel_pmc_gcr_read64(struct intel_pmc_dev *pmc, u32 offset, u64 *data);
0032 int intel_pmc_gcr_update(struct intel_pmc_dev *pmc, u32 offset, u32 mask, u32 val);
0033 int intel_pmc_s0ix_counter_read(struct intel_pmc_dev *pmc, u64 *data);
0034 #else
0035 static inline int intel_pmc_gcr_read64(struct intel_pmc_dev *pmc, u32 offset,
0036                        u64 *data)
0037 {
0038     return -ENOTSUPP;
0039 }
0040
0041 static inline int intel_pmc_gcr_update(struct intel_pmc_dev *pmc, u32 offset,
0042                        u32 mask, u32 val)
0043 {
0044     return -ENOTSUPP;
0045 }
0046
0047 static inline int intel_pmc_s0ix_counter_read(struct intel_pmc_dev *pmc, u64 *data)
0048 {
0049     return -ENOTSUPP;
0050 }
0051 #endif
0052
0053 #endif /* MFD_INTEL_PMC_BXT_H */