linux/mfd/intel-m10-bmc.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Intel MAX 10 Board Management Controller chip.
0004  *
0005  * Copyright (C) 2018-2020 Intel Corporation, Inc.
0006  */
0007 #ifndef __MFD_INTEL_M10_BMC_H
0008 #define __MFD_INTEL_M10_BMC_H
0009
0010 #include <linux/regmap.h>
0011
0012 #define M10BMC_LEGACY_BUILD_VER     0x300468
0013 #define M10BMC_SYS_BASE         0x300800
0014 #define M10BMC_SYS_END          0x300fff
0015 #define M10BMC_FLASH_BASE       0x10000000
0016 #define M10BMC_FLASH_END        0x1fffffff
0017 #define M10BMC_MEM_END          M10BMC_FLASH_END
0018
0019 #define M10BMC_STAGING_BASE     0x18000000
0020 #define M10BMC_STAGING_SIZE     0x3800000
0021
0022 /* Register offset of system registers */
0023 #define NIOS2_FW_VERSION        0x0
0024 #define M10BMC_MAC_LOW          0x10
0025 #define M10BMC_MAC_BYTE4        GENMASK(7, 0)
0026 #define M10BMC_MAC_BYTE3        GENMASK(15, 8)
0027 #define M10BMC_MAC_BYTE2        GENMASK(23, 16)
0028 #define M10BMC_MAC_BYTE1        GENMASK(31, 24)
0029 #define M10BMC_MAC_HIGH         0x14
0030 #define M10BMC_MAC_BYTE6        GENMASK(7, 0)
0031 #define M10BMC_MAC_BYTE5        GENMASK(15, 8)
0032 #define M10BMC_MAC_COUNT        GENMASK(23, 16)
0033 #define M10BMC_TEST_REG         0x3c
0034 #define M10BMC_BUILD_VER        0x68
0035 #define M10BMC_VER_MAJOR_MSK        GENMASK(23, 16)
0036 #define M10BMC_VER_PCB_INFO_MSK     GENMASK(31, 24)
0037 #define M10BMC_VER_LEGACY_INVALID   0xffffffff
0038
0039 /* Secure update doorbell register, in system register region */
0040 #define M10BMC_DOORBELL         0x400
0041
0042 /* Authorization Result register, in system register region */
0043 #define M10BMC_AUTH_RESULT      0x404
0044
0045 /* Doorbell register fields */
0046 #define DRBL_RSU_REQUEST        BIT(0)
0047 #define DRBL_RSU_PROGRESS       GENMASK(7, 4)
0048 #define DRBL_HOST_STATUS        GENMASK(11, 8)
0049 #define DRBL_RSU_STATUS         GENMASK(23, 16)
0050 #define DRBL_PKVL_EEPROM_LOAD_SEC   BIT(24)
0051 #define DRBL_PKVL1_POLL_EN      BIT(25)
0052 #define DRBL_PKVL2_POLL_EN      BIT(26)
0053 #define DRBL_CONFIG_SEL         BIT(28)
0054 #define DRBL_REBOOT_REQ         BIT(29)
0055 #define DRBL_REBOOT_DISABLED        BIT(30)
0056
0057 /* Progress states */
0058 #define RSU_PROG_IDLE           0x0
0059 #define RSU_PROG_PREPARE        0x1
0060 #define RSU_PROG_READY          0x3
0061 #define RSU_PROG_AUTHENTICATING     0x4
0062 #define RSU_PROG_COPYING        0x5
0063 #define RSU_PROG_UPDATE_CANCEL      0x6
0064 #define RSU_PROG_PROGRAM_KEY_HASH   0x7
0065 #define RSU_PROG_RSU_DONE       0x8
0066 #define RSU_PROG_PKVL_PROM_DONE     0x9
0067
0068 /* Device and error states */
0069 #define RSU_STAT_NORMAL         0x0
0070 #define RSU_STAT_TIMEOUT        0x1
0071 #define RSU_STAT_AUTH_FAIL      0x2
0072 #define RSU_STAT_COPY_FAIL      0x3
0073 #define RSU_STAT_FATAL          0x4
0074 #define RSU_STAT_PKVL_REJECT        0x5
0075 #define RSU_STAT_NON_INC        0x6
0076 #define RSU_STAT_ERASE_FAIL     0x7
0077 #define RSU_STAT_WEAROUT        0x8
0078 #define RSU_STAT_NIOS_OK        0x80
0079 #define RSU_STAT_USER_OK        0x81
0080 #define RSU_STAT_FACTORY_OK     0x82
0081 #define RSU_STAT_USER_FAIL      0x83
0082 #define RSU_STAT_FACTORY_FAIL       0x84
0083 #define RSU_STAT_NIOS_FLASH_ERR     0x85
0084 #define RSU_STAT_FPGA_FLASH_ERR     0x86
0085
0086 #define HOST_STATUS_IDLE        0x0
0087 #define HOST_STATUS_WRITE_DONE      0x1
0088 #define HOST_STATUS_ABORT_RSU       0x2
0089
0090 #define rsu_prog(doorbell)  FIELD_GET(DRBL_RSU_PROGRESS, doorbell)
0091 #define rsu_stat(doorbell)  FIELD_GET(DRBL_RSU_STATUS, doorbell)
0092
0093 /* interval 100ms and timeout 5s */
0094 #define NIOS_HANDSHAKE_INTERVAL_US  (100 * 1000)
0095 #define NIOS_HANDSHAKE_TIMEOUT_US   (5 * 1000 * 1000)
0096
0097 /* RSU PREP Timeout (2 minutes) to erase flash staging area */
0098 #define RSU_PREP_INTERVAL_MS        100
0099 #define RSU_PREP_TIMEOUT_MS     (2 * 60 * 1000)
0100
0101 /* RSU Complete Timeout (40 minutes) for full flash update */
0102 #define RSU_COMPLETE_INTERVAL_MS    1000
0103 #define RSU_COMPLETE_TIMEOUT_MS     (40 * 60 * 1000)
0104
0105 /* Addresses for security related data in FLASH */
0106 #define BMC_REH_ADDR    0x17ffc004
0107 #define BMC_PROG_ADDR   0x17ffc000
0108 #define BMC_PROG_MAGIC  0x5746
0109
0110 #define SR_REH_ADDR 0x17ffd004
0111 #define SR_PROG_ADDR    0x17ffd000
0112 #define SR_PROG_MAGIC   0x5253
0113
0114 #define PR_REH_ADDR 0x17ffe004
0115 #define PR_PROG_ADDR    0x17ffe000
0116 #define PR_PROG_MAGIC   0x5250
0117
0118 /* Address of 4KB inverted bit vector containing staging area FLASH count */
0119 #define STAGING_FLASH_COUNT 0x17ffb000
0120
0121 /**
0122  * struct intel_m10bmc - Intel MAX 10 BMC parent driver data structure
0123  * @dev: this device
0124  * @regmap: the regmap used to access registers by m10bmc itself
0125  */
0126 struct intel_m10bmc {
0127     struct device *dev;
0128     struct regmap *regmap;
0129 };
0130
0131 /*
0132  * register access helper functions.
0133  *
0134  * m10bmc_raw_read - read m10bmc register per addr
0135  * m10bmc_sys_read - read m10bmc system register per offset
0136  */
0137 static inline int
0138 m10bmc_raw_read(struct intel_m10bmc *m10bmc, unsigned int addr,
0139         unsigned int *val)
0140 {
0141     int ret;
0142
0143     ret = regmap_read(m10bmc->regmap, addr, val);
0144     if (ret)
0145         dev_err(m10bmc->dev, "fail to read raw reg %x: %d\n",
0146             addr, ret);
0147
0148     return ret;
0149 }
0150
0151 /*
0152  * The base of the system registers could be configured by HW developers, and
0153  * in HW SPEC, the base is not added to the addresses of the system registers.
0154  *
0155  * This macro helps to simplify the accessing of the system registers. And if
0156  * the base is reconfigured in HW, SW developers could simply change the
0157  * M10BMC_SYS_BASE accordingly.
0158  */
0159 #define m10bmc_sys_read(m10bmc, offset, val) \
0160     m10bmc_raw_read(m10bmc, M10BMC_SYS_BASE + (offset), val)
0161
0162 #endif /* __MFD_INTEL_M10_BMC_H */