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0005 #ifndef __LINUX_MFD_INGENIC_TCU_H_
0006 #define __LINUX_MFD_INGENIC_TCU_H_
0007
0008 #include <linux/bitops.h>
0009
0010 #define TCU_REG_WDT_TDR 0x00
0011 #define TCU_REG_WDT_TCER 0x04
0012 #define TCU_REG_WDT_TCNT 0x08
0013 #define TCU_REG_WDT_TCSR 0x0c
0014 #define TCU_REG_TER 0x10
0015 #define TCU_REG_TESR 0x14
0016 #define TCU_REG_TECR 0x18
0017 #define TCU_REG_TSR 0x1c
0018 #define TCU_REG_TFR 0x20
0019 #define TCU_REG_TFSR 0x24
0020 #define TCU_REG_TFCR 0x28
0021 #define TCU_REG_TSSR 0x2c
0022 #define TCU_REG_TMR 0x30
0023 #define TCU_REG_TMSR 0x34
0024 #define TCU_REG_TMCR 0x38
0025 #define TCU_REG_TSCR 0x3c
0026 #define TCU_REG_TDFR0 0x40
0027 #define TCU_REG_TDHR0 0x44
0028 #define TCU_REG_TCNT0 0x48
0029 #define TCU_REG_TCSR0 0x4c
0030 #define TCU_REG_OST_DR 0xe0
0031 #define TCU_REG_OST_CNTL 0xe4
0032 #define TCU_REG_OST_CNTH 0xe8
0033 #define TCU_REG_OST_TCSR 0xec
0034 #define TCU_REG_TSTR 0xf0
0035 #define TCU_REG_TSTSR 0xf4
0036 #define TCU_REG_TSTCR 0xf8
0037 #define TCU_REG_OST_CNTHBUF 0xfc
0038
0039 #define TCU_TCSR_RESERVED_BITS 0x3f
0040 #define TCU_TCSR_PARENT_CLOCK_MASK 0x07
0041 #define TCU_TCSR_PRESCALE_LSB 3
0042 #define TCU_TCSR_PRESCALE_MASK 0x38
0043
0044 #define TCU_TCSR_PWM_SD BIT(9)
0045 #define TCU_TCSR_PWM_INITL_HIGH BIT(8)
0046 #define TCU_TCSR_PWM_EN BIT(7)
0047
0048 #define TCU_WDT_TCER_TCEN BIT(0)
0049
0050 #define TCU_CHANNEL_STRIDE 0x10
0051 #define TCU_REG_TDFRc(c) (TCU_REG_TDFR0 + ((c) * TCU_CHANNEL_STRIDE))
0052 #define TCU_REG_TDHRc(c) (TCU_REG_TDHR0 + ((c) * TCU_CHANNEL_STRIDE))
0053 #define TCU_REG_TCNTc(c) (TCU_REG_TCNT0 + ((c) * TCU_CHANNEL_STRIDE))
0054 #define TCU_REG_TCSRc(c) (TCU_REG_TCSR0 + ((c) * TCU_CHANNEL_STRIDE))
0055
0056 #endif