linux/mfd/idt82p33_reg.h

0001 /* SPDX-License-Identifier: GPL-2.0+ */
0002 /*
0003  * Register Map - Based on AN888_SMUforIEEE_SynchEther_82P33xxx_RevH.pdf
0004  *
0005  * Copyright (C) 2021 Integrated Device Technology, Inc., a Renesas Company.
0006  */
0007 #ifndef HAVE_IDT82P33_REG
0008 #define HAVE_IDT82P33_REG
0009
0010 #define REG_ADDR(page, offset) (((page) << 0x7) | ((offset) & 0x7f))
0011
0012 /* Register address */
0013 #define DPLL1_TOD_CNFG 0x134
0014 #define DPLL2_TOD_CNFG 0x1B4
0015
0016 #define DPLL1_TOD_STS 0x10B
0017 #define DPLL2_TOD_STS 0x18B
0018
0019 #define DPLL1_TOD_TRIGGER 0x115
0020 #define DPLL2_TOD_TRIGGER 0x195
0021
0022 #define DPLL1_OPERATING_MODE_CNFG 0x120
0023 #define DPLL2_OPERATING_MODE_CNFG 0x1A0
0024
0025 #define DPLL1_HOLDOVER_FREQ_CNFG 0x12C
0026 #define DPLL2_HOLDOVER_FREQ_CNFG 0x1AC
0027
0028 #define DPLL1_PHASE_OFFSET_CNFG 0x143
0029 #define DPLL2_PHASE_OFFSET_CNFG 0x1C3
0030
0031 #define DPLL1_SYNC_EDGE_CNFG 0x140
0032 #define DPLL2_SYNC_EDGE_CNFG 0x1C0
0033
0034 #define DPLL1_INPUT_MODE_CNFG 0x116
0035 #define DPLL2_INPUT_MODE_CNFG 0x196
0036
0037 #define DPLL1_OPERATING_STS 0x102
0038 #define DPLL2_OPERATING_STS 0x182
0039
0040 #define DPLL1_CURRENT_FREQ_STS 0x103
0041 #define DPLL2_CURRENT_FREQ_STS 0x183
0042
0043 #define REG_SOFT_RESET 0X381
0044
0045 #define OUT_MUX_CNFG(outn) REG_ADDR(0x6, (0xC * (outn)))
0046 #define TOD_TRIGGER(wr_trig, rd_trig) ((wr_trig & 0xf) << 4 | (rd_trig & 0xf))
0047
0048 /* Register bit definitions */
0049 #define SYNC_TOD BIT(1)
0050 #define PH_OFFSET_EN BIT(7)
0051 #define SQUELCH_ENABLE BIT(5)
0052
0053 /* Bit definitions for the DPLL_MODE register */
0054 #define PLL_MODE_SHIFT      (0)
0055 #define PLL_MODE_MASK       (0x1F)
0056 #define COMBO_MODE_EN       BIT(5)
0057 #define COMBO_MODE_SHIFT    (6)
0058 #define COMBO_MODE_MASK     (0x3)
0059
0060 /* Bit definitions for DPLL_OPERATING_STS register */
0061 #define OPERATING_STS_MASK  (0x7)
0062 #define OPERATING_STS_SHIFT (0x0)
0063
0064 /* Bit definitions for DPLL_TOD_TRIGGER register */
0065 #define READ_TRIGGER_MASK   (0xF)
0066 #define READ_TRIGGER_SHIFT  (0x0)
0067 #define WRITE_TRIGGER_MASK  (0xF0)
0068 #define WRITE_TRIGGER_SHIFT (0x4)
0069
0070 /* Bit definitions for REG_SOFT_RESET register */
0071 #define SOFT_RESET_EN       BIT(7)
0072
0073 enum pll_mode {
0074     PLL_MODE_MIN = 0,
0075     PLL_MODE_AUTOMATIC = PLL_MODE_MIN,
0076     PLL_MODE_FORCE_FREERUN = 1,
0077     PLL_MODE_FORCE_HOLDOVER = 2,
0078     PLL_MODE_FORCE_LOCKED = 4,
0079     PLL_MODE_FORCE_PRE_LOCKED2 = 5,
0080     PLL_MODE_FORCE_PRE_LOCKED = 6,
0081     PLL_MODE_FORCE_LOST_PHASE = 7,
0082     PLL_MODE_DCO = 10,
0083     PLL_MODE_WPH = 18,
0084     PLL_MODE_MAX = PLL_MODE_WPH,
0085 };
0086
0087 enum hw_tod_trig_sel {
0088     HW_TOD_TRIG_SEL_MIN = 0,
0089     HW_TOD_TRIG_SEL_NO_WRITE = HW_TOD_TRIG_SEL_MIN,
0090     HW_TOD_TRIG_SEL_NO_READ = HW_TOD_TRIG_SEL_MIN,
0091     HW_TOD_TRIG_SEL_SYNC_SEL = 1,
0092     HW_TOD_TRIG_SEL_IN12 = 2,
0093     HW_TOD_TRIG_SEL_IN13 = 3,
0094     HW_TOD_TRIG_SEL_IN14 = 4,
0095     HW_TOD_TRIG_SEL_TOD_PPS = 5,
0096     HW_TOD_TRIG_SEL_TIMER_INTERVAL = 6,
0097     HW_TOD_TRIG_SEL_MSB_PHASE_OFFSET_CNFG = 7,
0098     HW_TOD_TRIG_SEL_MSB_HOLDOVER_FREQ_CNFG = 8,
0099     HW_TOD_WR_TRIG_SEL_MSB_TOD_CNFG = 9,
0100     HW_TOD_RD_TRIG_SEL_LSB_TOD_STS = HW_TOD_WR_TRIG_SEL_MSB_TOD_CNFG,
0101     WR_TRIG_SEL_MAX = HW_TOD_WR_TRIG_SEL_MSB_TOD_CNFG,
0102 };
0103
0104 /** @brief Enumerated type listing DPLL operational modes */
0105 enum dpll_state {
0106     DPLL_STATE_FREERUN = 1,
0107     DPLL_STATE_HOLDOVER = 2,
0108     DPLL_STATE_LOCKED = 4,
0109     DPLL_STATE_PRELOCKED2 = 5,
0110     DPLL_STATE_PRELOCKED = 6,
0111     DPLL_STATE_LOSTPHASE = 7,
0112     DPLL_STATE_MAX
0113 };
0114
0115 #endif