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0005 #ifndef __LINUX_MFD_GSC_H_
0006 #define __LINUX_MFD_GSC_H_
0007
0008 #include <linux/regmap.h>
0009
0010
0011 #define GSC_MISC 0x20
0012 #define GSC_UPDATE 0x21
0013 #define GSC_GPIO 0x23
0014 #define GSC_HWMON 0x29
0015 #define GSC_EEPROM0 0x50
0016 #define GSC_EEPROM1 0x51
0017 #define GSC_EEPROM2 0x52
0018 #define GSC_EEPROM3 0x53
0019 #define GSC_RTC 0x68
0020
0021
0022 enum {
0023 GSC_CTRL_0 = 0x00,
0024 GSC_CTRL_1 = 0x01,
0025 GSC_TIME = 0x02,
0026 GSC_TIME_ADD = 0x06,
0027 GSC_IRQ_STATUS = 0x0A,
0028 GSC_IRQ_ENABLE = 0x0B,
0029 GSC_FW_CRC = 0x0C,
0030 GSC_FW_VER = 0x0E,
0031 GSC_WP = 0x0F,
0032 };
0033
0034
0035 #define GSC_CTRL_0_PB_HARD_RESET 0
0036 #define GSC_CTRL_0_PB_CLEAR_SECURE_KEY 1
0037 #define GSC_CTRL_0_PB_SOFT_POWER_DOWN 2
0038 #define GSC_CTRL_0_PB_BOOT_ALTERNATE 3
0039 #define GSC_CTRL_0_PERFORM_CRC 4
0040 #define GSC_CTRL_0_TAMPER_DETECT 5
0041 #define GSC_CTRL_0_SWITCH_HOLD 6
0042
0043 #define GSC_CTRL_1_SLEEP_ENABLE 0
0044 #define GSC_CTRL_1_SLEEP_ACTIVATE 1
0045 #define GSC_CTRL_1_SLEEP_ADD 2
0046 #define GSC_CTRL_1_SLEEP_NOWAKEPB 3
0047 #define GSC_CTRL_1_WDT_TIME 4
0048 #define GSC_CTRL_1_WDT_ENABLE 5
0049 #define GSC_CTRL_1_SWITCH_BOOT_ENABLE 6
0050 #define GSC_CTRL_1_SWITCH_BOOT_CLEAR 7
0051
0052 #define GSC_IRQ_PB 0
0053 #define GSC_IRQ_KEY_ERASED 1
0054 #define GSC_IRQ_EEPROM_WP 2
0055 #define GSC_IRQ_RESV 3
0056 #define GSC_IRQ_GPIO 4
0057 #define GSC_IRQ_TAMPER 5
0058 #define GSC_IRQ_WDT_TIMEOUT 6
0059 #define GSC_IRQ_SWITCH_HOLD 7
0060
0061 int gsc_read(void *context, unsigned int reg, unsigned int *val);
0062 int gsc_write(void *context, unsigned int reg, unsigned int val);
0063
0064 struct gsc_dev {
0065 struct device *dev;
0066
0067 struct i2c_client *i2c;
0068 struct i2c_client *i2c_hwmon;
0069
0070 struct regmap *regmap;
0071
0072 unsigned int fwver;
0073 unsigned short fwcrc;
0074 };
0075
0076 #endif