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OSCL-LXR

 
 

    


0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* MFD cell driver data for the DS1WM driver
0003  *
0004  * to be defined in the MFD device that is
0005  * using this driver for one of his sub devices
0006  */
0007 
0008 struct ds1wm_driver_data {
0009     int active_high;
0010     int clock_rate;
0011     /* in milliseconds, the amount of time to
0012      * sleep following a reset pulse. Zero
0013      * should work if your bus devices recover
0014      * time respects the 1-wire spec since the
0015      * ds1wm implements the precise timings of
0016      * a reset pulse/presence detect sequence.
0017      */
0018     unsigned int reset_recover_delay;
0019 
0020     /* Say 1 here for big endian Hardware
0021      * (only relevant with bus-shift > 0
0022      */
0023     bool is_hw_big_endian;
0024 
0025     /* left shift of register number to get register address offsett.
0026      * Only 0,1,2 allowed for 8,16 or 32 bit bus width respectively
0027      */
0028     unsigned int bus_shift;
0029 };