linux/mfd/dbx500-prcmu.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (C) ST Ericsson SA 2011
0004  *
0005  * STE Ux500 PRCMU API
0006  */
0007 #ifndef __MACH_PRCMU_H
0008 #define __MACH_PRCMU_H
0009
0010 #include <linux/interrupt.h>
0011 #include <linux/notifier.h>
0012 #include <linux/err.h>
0013
0014 #include <dt-bindings/mfd/dbx500-prcmu.h> /* For clock identifiers */
0015
0016 /* Offset for the firmware version within the TCPM */
0017 #define DB8500_PRCMU_FW_VERSION_OFFSET 0xA4
0018 #define DBX540_PRCMU_FW_VERSION_OFFSET 0xA8
0019
0020 /* PRCMU Wakeup defines */
0021 enum prcmu_wakeup_index {
0022     PRCMU_WAKEUP_INDEX_RTC,
0023     PRCMU_WAKEUP_INDEX_RTT0,
0024     PRCMU_WAKEUP_INDEX_RTT1,
0025     PRCMU_WAKEUP_INDEX_HSI0,
0026     PRCMU_WAKEUP_INDEX_HSI1,
0027     PRCMU_WAKEUP_INDEX_USB,
0028     PRCMU_WAKEUP_INDEX_ABB,
0029     PRCMU_WAKEUP_INDEX_ABB_FIFO,
0030     PRCMU_WAKEUP_INDEX_ARM,
0031     PRCMU_WAKEUP_INDEX_CD_IRQ,
0032     NUM_PRCMU_WAKEUP_INDICES
0033 };
0034 #define PRCMU_WAKEUP(_name) (BIT(PRCMU_WAKEUP_INDEX_##_name))
0035
0036 /* EPOD (power domain) IDs */
0037
0038 /*
0039  * DB8500 EPODs
0040  * - EPOD_ID_SVAMMDSP: power domain for SVA MMDSP
0041  * - EPOD_ID_SVAPIPE: power domain for SVA pipe
0042  * - EPOD_ID_SIAMMDSP: power domain for SIA MMDSP
0043  * - EPOD_ID_SIAPIPE: power domain for SIA pipe
0044  * - EPOD_ID_SGA: power domain for SGA
0045  * - EPOD_ID_B2R2_MCDE: power domain for B2R2 and MCDE
0046  * - EPOD_ID_ESRAM12: power domain for ESRAM 1 and 2
0047  * - EPOD_ID_ESRAM34: power domain for ESRAM 3 and 4
0048  * - NUM_EPOD_ID: number of power domains
0049  *
0050  * TODO: These should be prefixed.
0051  */
0052 #define EPOD_ID_SVAMMDSP    0
0053 #define EPOD_ID_SVAPIPE     1
0054 #define EPOD_ID_SIAMMDSP    2
0055 #define EPOD_ID_SIAPIPE     3
0056 #define EPOD_ID_SGA     4
0057 #define EPOD_ID_B2R2_MCDE   5
0058 #define EPOD_ID_ESRAM12     6
0059 #define EPOD_ID_ESRAM34     7
0060 #define NUM_EPOD_ID     8
0061
0062 /*
0063  * state definition for EPOD (power domain)
0064  * - EPOD_STATE_NO_CHANGE: The EPOD should remain unchanged
0065  * - EPOD_STATE_OFF: The EPOD is switched off
0066  * - EPOD_STATE_RAMRET: The EPOD is switched off with its internal RAM in
0067  *                         retention
0068  * - EPOD_STATE_ON_CLK_OFF: The EPOD is switched on, clock is still off
0069  * - EPOD_STATE_ON: Same as above, but with clock enabled
0070  */
0071 #define EPOD_STATE_NO_CHANGE    0x00
0072 #define EPOD_STATE_OFF      0x01
0073 #define EPOD_STATE_RAMRET   0x02
0074 #define EPOD_STATE_ON_CLK_OFF   0x03
0075 #define EPOD_STATE_ON       0x04
0076
0077 /*
0078  * CLKOUT sources
0079  */
0080 #define PRCMU_CLKSRC_CLK38M     0x00
0081 #define PRCMU_CLKSRC_ACLK       0x01
0082 #define PRCMU_CLKSRC_SYSCLK     0x02
0083 #define PRCMU_CLKSRC_LCDCLK     0x03
0084 #define PRCMU_CLKSRC_SDMMCCLK       0x04
0085 #define PRCMU_CLKSRC_TVCLK      0x05
0086 #define PRCMU_CLKSRC_TIMCLK     0x06
0087 #define PRCMU_CLKSRC_CLK009     0x07
0088 /* These are only valid for CLKOUT1: */
0089 #define PRCMU_CLKSRC_SIAMMDSPCLK    0x40
0090 #define PRCMU_CLKSRC_I2CCLK     0x41
0091 #define PRCMU_CLKSRC_MSP02CLK       0x42
0092 #define PRCMU_CLKSRC_ARMPLL_OBSCLK  0x43
0093 #define PRCMU_CLKSRC_HSIRXCLK       0x44
0094 #define PRCMU_CLKSRC_HSITXCLK       0x45
0095 #define PRCMU_CLKSRC_ARMCLKFIX      0x46
0096 #define PRCMU_CLKSRC_HDMICLK        0x47
0097
0098 /**
0099  * enum prcmu_wdog_id - PRCMU watchdog IDs
0100  * @PRCMU_WDOG_ALL: use all timers
0101  * @PRCMU_WDOG_CPU1: use first CPU timer only
0102  * @PRCMU_WDOG_CPU2: use second CPU timer conly
0103  */
0104 enum prcmu_wdog_id {
0105     PRCMU_WDOG_ALL = 0x00,
0106     PRCMU_WDOG_CPU1 = 0x01,
0107     PRCMU_WDOG_CPU2 = 0x02,
0108 };
0109
0110 /**
0111  * enum ape_opp - APE OPP states definition
0112  * @APE_OPP_INIT:
0113  * @APE_NO_CHANGE: The APE operating point is unchanged
0114  * @APE_100_OPP: The new APE operating point is ape100opp
0115  * @APE_50_OPP: 50%
0116  * @APE_50_PARTLY_25_OPP: 50%, except some clocks at 25%.
0117  */
0118 enum ape_opp {
0119     APE_OPP_INIT = 0x00,
0120     APE_NO_CHANGE = 0x01,
0121     APE_100_OPP = 0x02,
0122     APE_50_OPP = 0x03,
0123     APE_50_PARTLY_25_OPP = 0xFF,
0124 };
0125
0126 /**
0127  * enum arm_opp - ARM OPP states definition
0128  * @ARM_OPP_INIT:
0129  * @ARM_NO_CHANGE: The ARM operating point is unchanged
0130  * @ARM_100_OPP: The new ARM operating point is arm100opp
0131  * @ARM_50_OPP: The new ARM operating point is arm50opp
0132  * @ARM_MAX_OPP: Operating point is "max" (more than 100)
0133  * @ARM_MAX_FREQ100OPP: Set max opp if available, else 100
0134  * @ARM_EXTCLK: The new ARM operating point is armExtClk
0135  */
0136 enum arm_opp {
0137     ARM_OPP_INIT = 0x00,
0138     ARM_NO_CHANGE = 0x01,
0139     ARM_100_OPP = 0x02,
0140     ARM_50_OPP = 0x03,
0141     ARM_MAX_OPP = 0x04,
0142     ARM_MAX_FREQ100OPP = 0x05,
0143     ARM_EXTCLK = 0x07
0144 };
0145
0146 /**
0147  * enum ddr_opp - DDR OPP states definition
0148  * @DDR_100_OPP: The new DDR operating point is ddr100opp
0149  * @DDR_50_OPP: The new DDR operating point is ddr50opp
0150  * @DDR_25_OPP: The new DDR operating point is ddr25opp
0151  */
0152 enum ddr_opp {
0153     DDR_100_OPP = 0x00,
0154     DDR_50_OPP = 0x01,
0155     DDR_25_OPP = 0x02,
0156 };
0157
0158 /*
0159  * Definitions for controlling ESRAM0 in deep sleep.
0160  */
0161 #define ESRAM0_DEEP_SLEEP_STATE_OFF 1
0162 #define ESRAM0_DEEP_SLEEP_STATE_RET 2
0163
0164 /**
0165  * enum ddr_pwrst - DDR power states definition
0166  * @DDR_PWR_STATE_UNCHANGED: SDRAM and DDR controller state is unchanged
0167  * @DDR_PWR_STATE_ON:
0168  * @DDR_PWR_STATE_OFFLOWLAT:
0169  * @DDR_PWR_STATE_OFFHIGHLAT:
0170  */
0171 enum ddr_pwrst {
0172     DDR_PWR_STATE_UNCHANGED     = 0x00,
0173     DDR_PWR_STATE_ON            = 0x01,
0174     DDR_PWR_STATE_OFFLOWLAT     = 0x02,
0175     DDR_PWR_STATE_OFFHIGHLAT    = 0x03
0176 };
0177
0178 #define DB8500_PRCMU_LEGACY_OFFSET      0xDD4
0179
0180 #define PRCMU_FW_PROJECT_U8500      2
0181 #define PRCMU_FW_PROJECT_U8400      3
0182 #define PRCMU_FW_PROJECT_U9500      4 /* Customer specific */
0183 #define PRCMU_FW_PROJECT_U8500_MBB  5
0184 #define PRCMU_FW_PROJECT_U8500_C1   6
0185 #define PRCMU_FW_PROJECT_U8500_C2   7
0186 #define PRCMU_FW_PROJECT_U8500_C3   8
0187 #define PRCMU_FW_PROJECT_U8500_C4   9
0188 #define PRCMU_FW_PROJECT_U9500_MBL  10
0189 #define PRCMU_FW_PROJECT_U8500_SSG1 11 /* Samsung specific */
0190 #define PRCMU_FW_PROJECT_U8500_MBL2 12 /* Customer specific */
0191 #define PRCMU_FW_PROJECT_U8520      13
0192 #define PRCMU_FW_PROJECT_U8420      14
0193 #define PRCMU_FW_PROJECT_U8500_SSG2 15 /* Samsung specific */
0194 #define PRCMU_FW_PROJECT_U8420_SYSCLK   17
0195 #define PRCMU_FW_PROJECT_A9420      20
0196 /* [32..63] 9540 and derivatives */
0197 #define PRCMU_FW_PROJECT_U9540      32
0198 /* [64..95] 8540 and derivatives */
0199 #define PRCMU_FW_PROJECT_L8540      64
0200 /* [96..126] 8580 and derivatives */
0201 #define PRCMU_FW_PROJECT_L8580      96
0202
0203 #define PRCMU_FW_PROJECT_NAME_LEN   20
0204 struct prcmu_fw_version {
0205     u32 project; /* Notice, project shifted with 8 on ux540 */
0206     u8 api_version;
0207     u8 func_version;
0208     u8 errata;
0209     char project_name[PRCMU_FW_PROJECT_NAME_LEN];
0210 };
0211
0212 #include <linux/mfd/db8500-prcmu.h>
0213
0214 #if defined(CONFIG_UX500_SOC_DB8500)
0215
0216 static inline void prcmu_early_init(void)
0217 {
0218     return db8500_prcmu_early_init();
0219 }
0220
0221 static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk,
0222         bool keep_ap_pll)
0223 {
0224     return db8500_prcmu_set_power_state(state, keep_ulp_clk,
0225         keep_ap_pll);
0226 }
0227
0228 static inline u8 prcmu_get_power_state_result(void)
0229 {
0230     return db8500_prcmu_get_power_state_result();
0231 }
0232
0233 static inline int prcmu_set_epod(u16 epod_id, u8 epod_state)
0234 {
0235     return db8500_prcmu_set_epod(epod_id, epod_state);
0236 }
0237
0238 static inline void prcmu_enable_wakeups(u32 wakeups)
0239 {
0240     db8500_prcmu_enable_wakeups(wakeups);
0241 }
0242
0243 static inline void prcmu_disable_wakeups(void)
0244 {
0245     prcmu_enable_wakeups(0);
0246 }
0247
0248 static inline void prcmu_config_abb_event_readout(u32 abb_events)
0249 {
0250     db8500_prcmu_config_abb_event_readout(abb_events);
0251 }
0252
0253 static inline void prcmu_get_abb_event_buffer(void __iomem **buf)
0254 {
0255     db8500_prcmu_get_abb_event_buffer(buf);
0256 }
0257
0258 int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size);
0259 int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size);
0260 int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value, u8 *mask, u8 size);
0261
0262 int prcmu_config_clkout(u8 clkout, u8 source, u8 div);
0263
0264 static inline int prcmu_request_clock(u8 clock, bool enable)
0265 {
0266     return db8500_prcmu_request_clock(clock, enable);
0267 }
0268
0269 unsigned long prcmu_clock_rate(u8 clock);
0270 long prcmu_round_clock_rate(u8 clock, unsigned long rate);
0271 int prcmu_set_clock_rate(u8 clock, unsigned long rate);
0272
0273 static inline int prcmu_get_ddr_opp(void)
0274 {
0275     return db8500_prcmu_get_ddr_opp();
0276 }
0277
0278 static inline int prcmu_set_arm_opp(u8 opp)
0279 {
0280     return db8500_prcmu_set_arm_opp(opp);
0281 }
0282
0283 static inline int prcmu_get_arm_opp(void)
0284 {
0285     return db8500_prcmu_get_arm_opp();
0286 }
0287
0288 static inline int prcmu_set_ape_opp(u8 opp)
0289 {
0290     return db8500_prcmu_set_ape_opp(opp);
0291 }
0292
0293 static inline int prcmu_get_ape_opp(void)
0294 {
0295     return db8500_prcmu_get_ape_opp();
0296 }
0297
0298 static inline int prcmu_request_ape_opp_100_voltage(bool enable)
0299 {
0300     return db8500_prcmu_request_ape_opp_100_voltage(enable);
0301 }
0302
0303 static inline void prcmu_system_reset(u16 reset_code)
0304 {
0305     return db8500_prcmu_system_reset(reset_code);
0306 }
0307
0308 static inline u16 prcmu_get_reset_code(void)
0309 {
0310     return db8500_prcmu_get_reset_code();
0311 }
0312
0313 int prcmu_ac_wake_req(void);
0314 void prcmu_ac_sleep_req(void);
0315 static inline void prcmu_modem_reset(void)
0316 {
0317     return db8500_prcmu_modem_reset();
0318 }
0319
0320 static inline bool prcmu_is_ac_wake_requested(void)
0321 {
0322     return db8500_prcmu_is_ac_wake_requested();
0323 }
0324
0325 static inline int prcmu_config_esram0_deep_sleep(u8 state)
0326 {
0327     return db8500_prcmu_config_esram0_deep_sleep(state);
0328 }
0329
0330 static inline int prcmu_config_hotdog(u8 threshold)
0331 {
0332     return db8500_prcmu_config_hotdog(threshold);
0333 }
0334
0335 static inline int prcmu_config_hotmon(u8 low, u8 high)
0336 {
0337     return db8500_prcmu_config_hotmon(low, high);
0338 }
0339
0340 static inline int prcmu_start_temp_sense(u16 cycles32k)
0341 {
0342     return  db8500_prcmu_start_temp_sense(cycles32k);
0343 }
0344
0345 static inline int prcmu_stop_temp_sense(void)
0346 {
0347     return  db8500_prcmu_stop_temp_sense();
0348 }
0349
0350 static inline u32 prcmu_read(unsigned int reg)
0351 {
0352     return db8500_prcmu_read(reg);
0353 }
0354
0355 static inline void prcmu_write(unsigned int reg, u32 value)
0356 {
0357     db8500_prcmu_write(reg, value);
0358 }
0359
0360 static inline void prcmu_write_masked(unsigned int reg, u32 mask, u32 value)
0361 {
0362     db8500_prcmu_write_masked(reg, mask, value);
0363 }
0364
0365 static inline int prcmu_enable_a9wdog(u8 id)
0366 {
0367     return db8500_prcmu_enable_a9wdog(id);
0368 }
0369
0370 static inline int prcmu_disable_a9wdog(u8 id)
0371 {
0372     return db8500_prcmu_disable_a9wdog(id);
0373 }
0374
0375 static inline int prcmu_kick_a9wdog(u8 id)
0376 {
0377     return db8500_prcmu_kick_a9wdog(id);
0378 }
0379
0380 static inline int prcmu_load_a9wdog(u8 id, u32 timeout)
0381 {
0382     return db8500_prcmu_load_a9wdog(id, timeout);
0383 }
0384
0385 static inline int prcmu_config_a9wdog(u8 num, bool sleep_auto_off)
0386 {
0387     return db8500_prcmu_config_a9wdog(num, sleep_auto_off);
0388 }
0389 #else
0390
0391 static inline void prcmu_early_init(void) {}
0392
0393 static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk,
0394     bool keep_ap_pll)
0395 {
0396     return 0;
0397 }
0398
0399 static inline int prcmu_set_epod(u16 epod_id, u8 epod_state)
0400 {
0401     return 0;
0402 }
0403
0404 static inline void prcmu_enable_wakeups(u32 wakeups) {}
0405
0406 static inline void prcmu_disable_wakeups(void) {}
0407
0408 static inline int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
0409 {
0410     return -ENOSYS;
0411 }
0412
0413 static inline int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
0414 {
0415     return -ENOSYS;
0416 }
0417
0418 static inline int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value, u8 *mask,
0419     u8 size)
0420 {
0421     return -ENOSYS;
0422 }
0423
0424 static inline int prcmu_config_clkout(u8 clkout, u8 source, u8 div)
0425 {
0426     return 0;
0427 }
0428
0429 static inline int prcmu_request_clock(u8 clock, bool enable)
0430 {
0431     return 0;
0432 }
0433
0434 static inline long prcmu_round_clock_rate(u8 clock, unsigned long rate)
0435 {
0436     return 0;
0437 }
0438
0439 static inline int prcmu_set_clock_rate(u8 clock, unsigned long rate)
0440 {
0441     return 0;
0442 }
0443
0444 static inline unsigned long prcmu_clock_rate(u8 clock)
0445 {
0446     return 0;
0447 }
0448
0449 static inline int prcmu_set_ape_opp(u8 opp)
0450 {
0451     return 0;
0452 }
0453
0454 static inline int prcmu_get_ape_opp(void)
0455 {
0456     return APE_100_OPP;
0457 }
0458
0459 static inline int prcmu_request_ape_opp_100_voltage(bool enable)
0460 {
0461     return 0;
0462 }
0463
0464 static inline int prcmu_set_arm_opp(u8 opp)
0465 {
0466     return 0;
0467 }
0468
0469 static inline int prcmu_get_arm_opp(void)
0470 {
0471     return ARM_100_OPP;
0472 }
0473
0474 static inline int prcmu_get_ddr_opp(void)
0475 {
0476     return DDR_100_OPP;
0477 }
0478
0479 static inline void prcmu_system_reset(u16 reset_code) {}
0480
0481 static inline u16 prcmu_get_reset_code(void)
0482 {
0483     return 0;
0484 }
0485
0486 static inline int prcmu_ac_wake_req(void)
0487 {
0488     return 0;
0489 }
0490
0491 static inline void prcmu_ac_sleep_req(void) {}
0492
0493 static inline void prcmu_modem_reset(void) {}
0494
0495 static inline bool prcmu_is_ac_wake_requested(void)
0496 {
0497     return false;
0498 }
0499
0500 static inline int prcmu_config_esram0_deep_sleep(u8 state)
0501 {
0502     return 0;
0503 }
0504
0505 static inline void prcmu_config_abb_event_readout(u32 abb_events) {}
0506
0507 static inline void prcmu_get_abb_event_buffer(void __iomem **buf)
0508 {
0509     *buf = NULL;
0510 }
0511
0512 static inline int prcmu_config_hotdog(u8 threshold)
0513 {
0514     return 0;
0515 }
0516
0517 static inline int prcmu_config_hotmon(u8 low, u8 high)
0518 {
0519     return 0;
0520 }
0521
0522 static inline int prcmu_start_temp_sense(u16 cycles32k)
0523 {
0524     return 0;
0525 }
0526
0527 static inline int prcmu_stop_temp_sense(void)
0528 {
0529     return 0;
0530 }
0531
0532 static inline u32 prcmu_read(unsigned int reg)
0533 {
0534     return 0;
0535 }
0536
0537 static inline void prcmu_write(unsigned int reg, u32 value) {}
0538
0539 static inline void prcmu_write_masked(unsigned int reg, u32 mask, u32 value) {}
0540
0541 #endif
0542
0543 static inline void prcmu_set(unsigned int reg, u32 bits)
0544 {
0545     prcmu_write_masked(reg, bits, bits);
0546 }
0547
0548 static inline void prcmu_clear(unsigned int reg, u32 bits)
0549 {
0550     prcmu_write_masked(reg, bits, 0);
0551 }
0552
0553 /* PRCMU QoS APE OPP class */
0554 #define PRCMU_QOS_APE_OPP 1
0555 #define PRCMU_QOS_DDR_OPP 2
0556 #define PRCMU_QOS_ARM_OPP 3
0557 #define PRCMU_QOS_DEFAULT_VALUE -1
0558
0559 static inline unsigned long prcmu_qos_get_cpufreq_opp_delay(void)
0560 {
0561     return 0;
0562 }
0563
0564 static inline int prcmu_qos_requirement(int prcmu_qos_class)
0565 {
0566     return 0;
0567 }
0568
0569 static inline int prcmu_qos_add_requirement(int prcmu_qos_class,
0570                         char *name, s32 value)
0571 {
0572     return 0;
0573 }
0574
0575 static inline int prcmu_qos_update_requirement(int prcmu_qos_class,
0576                            char *name, s32 new_value)
0577 {
0578     return 0;
0579 }
0580
0581 static inline void prcmu_qos_remove_requirement(int prcmu_qos_class, char *name)
0582 {
0583 }
0584
0585 static inline int prcmu_qos_add_notifier(int prcmu_qos_class,
0586                      struct notifier_block *notifier)
0587 {
0588     return 0;
0589 }
0590 static inline int prcmu_qos_remove_notifier(int prcmu_qos_class,
0591                         struct notifier_block *notifier)
0592 {
0593     return 0;
0594 }
0595
0596 #endif /* __MACH_PRCMU_H */