linux/mfd/db8500-prcmu.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (C) STMicroelectronics 2009
0004  * Copyright (C) ST-Ericsson SA 2010
0005  *
0006  * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com>
0007  *
0008  * PRCMU f/w APIs
0009  */
0010 #ifndef __MFD_DB8500_PRCMU_H
0011 #define __MFD_DB8500_PRCMU_H
0012
0013 #include <linux/interrupt.h>
0014 #include <linux/bitops.h>
0015
0016 /*
0017  * Registers
0018  */
0019 #define DB8500_PRCM_LINE_VALUE 0x170
0020 #define DB8500_PRCM_LINE_VALUE_HSI_CAWAKE0  BIT(3)
0021
0022 #define DB8500_PRCM_DSI_SW_RESET 0x324
0023 #define DB8500_PRCM_DSI_SW_RESET_DSI0_SW_RESETN BIT(0)
0024 #define DB8500_PRCM_DSI_SW_RESET_DSI1_SW_RESETN BIT(1)
0025 #define DB8500_PRCM_DSI_SW_RESET_DSI2_SW_RESETN BIT(2)
0026
0027 /* This portion previously known as <mach/prcmu-fw-defs_v1.h> */
0028
0029 /**
0030  * enum state - ON/OFF state definition
0031  * @OFF: State is ON
0032  * @ON: State is OFF
0033  *
0034  */
0035 enum state {
0036     OFF = 0x0,
0037     ON  = 0x1,
0038 };
0039
0040 /**
0041  * enum ret_state - general purpose On/Off/Retention states
0042  *
0043  */
0044 enum ret_state {
0045     OFFST = 0,
0046     ONST  = 1,
0047     RETST = 2
0048 };
0049
0050 /**
0051  * enum clk_arm - ARM Cortex A9 clock schemes
0052  * @A9_OFF:
0053  * @A9_BOOT:
0054  * @A9_OPPT1:
0055  * @A9_OPPT2:
0056  * @A9_EXTCLK:
0057  */
0058 enum clk_arm {
0059     A9_OFF,
0060     A9_BOOT,
0061     A9_OPPT1,
0062     A9_OPPT2,
0063     A9_EXTCLK
0064 };
0065
0066 /**
0067  * enum clk_gen - GEN#0/GEN#1 clock schemes
0068  * @GEN_OFF:
0069  * @GEN_BOOT:
0070  * @GEN_OPPT1:
0071  */
0072 enum clk_gen {
0073     GEN_OFF,
0074     GEN_BOOT,
0075     GEN_OPPT1,
0076 };
0077
0078 /* some information between arm and xp70 */
0079
0080 /**
0081  * enum romcode_write - Romcode message written by A9 AND read by XP70
0082  * @RDY_2_DS: Value set when ApDeepSleep state can be executed by XP70
0083  * @RDY_2_XP70_RST: Value set when 0x0F has been successfully polled by the
0084  *                 romcode. The xp70 will go into self-reset
0085  */
0086 enum romcode_write {
0087     RDY_2_DS = 0x09,
0088     RDY_2_XP70_RST = 0x10
0089 };
0090
0091 /**
0092  * enum romcode_read - Romcode message written by XP70 and read by A9
0093  * @INIT: Init value when romcode field is not used
0094  * @FS_2_DS: Value set when power state is going from ApExecute to
0095  *          ApDeepSleep
0096  * @END_DS: Value set when ApDeepSleep power state is reached coming from
0097  *         ApExecute state
0098  * @DS_TO_FS: Value set when power state is going from ApDeepSleep to
0099  *           ApExecute
0100  * @END_FS: Value set when ApExecute power state is reached coming from
0101  *         ApDeepSleep state
0102  * @SWR: Value set when power state is going to ApReset
0103  * @END_SWR: Value set when the xp70 finished executing ApReset actions and
0104  *          waits for romcode acknowledgment to go to self-reset
0105  */
0106 enum romcode_read {
0107     INIT = 0x00,
0108     FS_2_DS = 0x0A,
0109     END_DS = 0x0B,
0110     DS_TO_FS = 0x0C,
0111     END_FS = 0x0D,
0112     SWR = 0x0E,
0113     END_SWR = 0x0F
0114 };
0115
0116 /**
0117  * enum ap_pwrst - current power states defined in PRCMU firmware
0118  * @NO_PWRST: Current power state init
0119  * @AP_BOOT: Current power state is apBoot
0120  * @AP_EXECUTE: Current power state is apExecute
0121  * @AP_DEEP_SLEEP: Current power state is apDeepSleep
0122  * @AP_SLEEP: Current power state is apSleep
0123  * @AP_IDLE: Current power state is apIdle
0124  * @AP_RESET: Current power state is apReset
0125  */
0126 enum ap_pwrst {
0127     NO_PWRST = 0x00,
0128     AP_BOOT = 0x01,
0129     AP_EXECUTE = 0x02,
0130     AP_DEEP_SLEEP = 0x03,
0131     AP_SLEEP = 0x04,
0132     AP_IDLE = 0x05,
0133     AP_RESET = 0x06
0134 };
0135
0136 /**
0137  * enum ap_pwrst_trans - Transition states defined in PRCMU firmware
0138  * @NO_TRANSITION: No power state transition
0139  * @APEXECUTE_TO_APSLEEP: Power state transition from ApExecute to ApSleep
0140  * @APIDLE_TO_APSLEEP: Power state transition from ApIdle to ApSleep
0141  * @APBOOT_TO_APEXECUTE: Power state transition from ApBoot to ApExecute
0142  * @APEXECUTE_TO_APDEEPSLEEP: Power state transition from ApExecute to
0143  *                          ApDeepSleep
0144  * @APEXECUTE_TO_APIDLE: Power state transition from ApExecute to ApIdle
0145  */
0146 enum ap_pwrst_trans {
0147     PRCMU_AP_NO_CHANGE      = 0x00,
0148     APEXECUTE_TO_APSLEEP        = 0x01,
0149     APIDLE_TO_APSLEEP       = 0x02, /* To be removed */
0150     PRCMU_AP_SLEEP          = 0x01,
0151     APBOOT_TO_APEXECUTE     = 0x03,
0152     APEXECUTE_TO_APDEEPSLEEP    = 0x04, /* To be removed */
0153     PRCMU_AP_DEEP_SLEEP     = 0x04,
0154     APEXECUTE_TO_APIDLE     = 0x05, /* To be removed */
0155     PRCMU_AP_IDLE           = 0x05,
0156     PRCMU_AP_DEEP_IDLE      = 0x07,
0157 };
0158
0159 /**
0160  * enum hw_acc_state - State definition for hardware accelerator
0161  * @HW_NO_CHANGE: The hardware accelerator state must remain unchanged
0162  * @HW_OFF: The hardware accelerator must be switched off
0163  * @HW_OFF_RAMRET: The hardware accelerator must be switched off with its
0164  *               internal RAM in retention
0165  * @HW_ON: The hwa hardware accelerator hwa must be switched on
0166  *
0167  * NOTE! Deprecated, to be removed when all users switched over to use the
0168  * regulator API.
0169  */
0170 enum hw_acc_state {
0171     HW_NO_CHANGE = 0x00,
0172     HW_OFF = 0x01,
0173     HW_OFF_RAMRET = 0x02,
0174     HW_ON = 0x04
0175 };
0176
0177 /**
0178  * enum  mbox_2_arm_stat - Status messages definition for mbox_arm
0179  * @BOOT_TO_EXECUTEOK: The apBoot to apExecute state transition has been
0180  *                    completed
0181  * @DEEPSLEEPOK: The apExecute to apDeepSleep state transition has been
0182  *              completed
0183  * @SLEEPOK: The apExecute to apSleep state transition has been completed
0184  * @IDLEOK: The apExecute to apIdle state transition has been completed
0185  * @SOFTRESETOK: The A9 watchdog/ SoftReset state has been completed
0186  * @SOFTRESETGO : The A9 watchdog/SoftReset state is on going
0187  * @BOOT_TO_EXECUTE: The apBoot to apExecute state transition is on going
0188  * @EXECUTE_TO_DEEPSLEEP: The apExecute to apDeepSleep state transition is on
0189  *                       going
0190  * @DEEPSLEEP_TO_EXECUTE: The apDeepSleep to apExecute state transition is on
0191  *                       going
0192  * @DEEPSLEEP_TO_EXECUTEOK: The apDeepSleep to apExecute state transition has
0193  *                         been completed
0194  * @EXECUTE_TO_SLEEP: The apExecute to apSleep state transition is on going
0195  * @SLEEP_TO_EXECUTE: The apSleep to apExecute state transition is on going
0196  * @SLEEP_TO_EXECUTEOK: The apSleep to apExecute state transition has been
0197  *                     completed
0198  * @EXECUTE_TO_IDLE: The apExecute to apIdle state transition is on going
0199  * @IDLE_TO_EXECUTE: The apIdle to apExecute state transition is on going
0200  * @IDLE_TO_EXECUTEOK: The apIdle to apExecute state transition has been
0201  *                    completed
0202  * @INIT_STATUS: Status init
0203  */
0204 enum ap_pwrsttr_status {
0205     BOOT_TO_EXECUTEOK = 0xFF,
0206     DEEPSLEEPOK = 0xFE,
0207     SLEEPOK = 0xFD,
0208     IDLEOK = 0xFC,
0209     SOFTRESETOK = 0xFB,
0210     SOFTRESETGO = 0xFA,
0211     BOOT_TO_EXECUTE = 0xF9,
0212     EXECUTE_TO_DEEPSLEEP = 0xF8,
0213     DEEPSLEEP_TO_EXECUTE = 0xF7,
0214     DEEPSLEEP_TO_EXECUTEOK = 0xF6,
0215     EXECUTE_TO_SLEEP = 0xF5,
0216     SLEEP_TO_EXECUTE = 0xF4,
0217     SLEEP_TO_EXECUTEOK = 0xF3,
0218     EXECUTE_TO_IDLE = 0xF2,
0219     IDLE_TO_EXECUTE = 0xF1,
0220     IDLE_TO_EXECUTEOK = 0xF0,
0221     RDYTODS_RETURNTOEXE    = 0xEF,
0222     NORDYTODS_RETURNTOEXE  = 0xEE,
0223     EXETOSLEEP_RETURNTOEXE = 0xED,
0224     EXETOIDLE_RETURNTOEXE  = 0xEC,
0225     INIT_STATUS = 0xEB,
0226
0227     /*error messages */
0228     INITERROR                     = 0x00,
0229     PLLARMLOCKP_ER                = 0x01,
0230     PLLDDRLOCKP_ER                = 0x02,
0231     PLLSOCLOCKP_ER                = 0x03,
0232     PLLSOCK1LOCKP_ER              = 0x04,
0233     ARMWFI_ER                     = 0x05,
0234     SYSCLKOK_ER                   = 0x06,
0235     I2C_NACK_DATA_ER              = 0x07,
0236     BOOT_ER                       = 0x08,
0237     I2C_STATUS_ALWAYS_1           = 0x0A,
0238     I2C_NACK_REG_ADDR_ER          = 0x0B,
0239     I2C_NACK_DATA0123_ER          = 0x1B,
0240     I2C_NACK_ADDR_ER              = 0x1F,
0241     CURAPPWRSTISNOT_BOOT          = 0x20,
0242     CURAPPWRSTISNOT_EXECUTE       = 0x21,
0243     CURAPPWRSTISNOT_SLEEPMODE     = 0x22,
0244     CURAPPWRSTISNOT_CORRECTFORIT10 = 0x23,
0245     FIFO4500WUISNOT_WUPEVENT      = 0x24,
0246     PLL32KLOCKP_ER                = 0x29,
0247     DDRDEEPSLEEPOK_ER             = 0x2A,
0248     ROMCODEREADY_ER               = 0x50,
0249     WUPBEFOREDS                   = 0x51,
0250     DDRCONFIG_ER                  = 0x52,
0251     WUPBEFORESLEEP                = 0x53,
0252     WUPBEFOREIDLE                 = 0x54
0253 };  /* earlier called as  mbox_2_arm_stat */
0254
0255 /**
0256  * enum dvfs_stat - DVFS status messages definition
0257  * @DVFS_GO: A state transition DVFS is on going
0258  * @DVFS_ARM100OPPOK: The state transition DVFS has been completed for 100OPP
0259  * @DVFS_ARM50OPPOK: The state transition DVFS has been completed for 50OPP
0260  * @DVFS_ARMEXTCLKOK: The state transition DVFS has been completed for EXTCLK
0261  * @DVFS_NOCHGTCLKOK: The state transition DVFS has been completed for
0262  *                   NOCHGCLK
0263  * @DVFS_INITSTATUS: Value init
0264  */
0265 enum dvfs_stat {
0266     DVFS_GO = 0xFF,
0267     DVFS_ARM100OPPOK = 0xFE,
0268     DVFS_ARM50OPPOK = 0xFD,
0269     DVFS_ARMEXTCLKOK = 0xFC,
0270     DVFS_NOCHGTCLKOK = 0xFB,
0271     DVFS_INITSTATUS = 0x00
0272 };
0273
0274 /**
0275  * enum sva_mmdsp_stat - SVA MMDSP status messages
0276  * @SVA_MMDSP_GO: SVAMMDSP interrupt has happened
0277  * @SVA_MMDSP_INIT: Status init
0278  */
0279 enum sva_mmdsp_stat {
0280     SVA_MMDSP_GO = 0xFF,
0281     SVA_MMDSP_INIT = 0x00
0282 };
0283
0284 /**
0285  * enum sia_mmdsp_stat - SIA MMDSP status messages
0286  * @SIA_MMDSP_GO: SIAMMDSP interrupt has happened
0287  * @SIA_MMDSP_INIT: Status init
0288  */
0289 enum sia_mmdsp_stat {
0290     SIA_MMDSP_GO = 0xFF,
0291     SIA_MMDSP_INIT = 0x00
0292 };
0293
0294 /**
0295  * enum  mbox_to_arm_err - Error messages definition
0296  * @INIT_ERR: Init value
0297  * @PLLARMLOCKP_ERR: PLLARM has not been correctly locked in given time
0298  * @PLLDDRLOCKP_ERR: PLLDDR has not been correctly locked in the given time
0299  * @PLLSOC0LOCKP_ERR: PLLSOC0 has not been correctly locked in the given time
0300  * @PLLSOC1LOCKP_ERR: PLLSOC1 has not been correctly locked in the given time
0301  * @ARMWFI_ERR: The ARM WFI has not been correctly executed in the given time
0302  * @SYSCLKOK_ERR: The SYSCLK is not available in the given time
0303  * @BOOT_ERR: Romcode has not validated the XP70 self reset in the given time
0304  * @ROMCODESAVECONTEXT: The Romcode didn.t correctly save it secure context
0305  * @VARMHIGHSPEEDVALTO_ERR: The ARM high speed supply value transfered
0306  *          through I2C has not been correctly executed in the given time
0307  * @VARMHIGHSPEEDACCESS_ERR: The command value of VarmHighSpeedVal transfered
0308  *             through I2C has not been correctly executed in the given time
0309  * @VARMLOWSPEEDVALTO_ERR:The ARM low speed supply value transfered through
0310  *                     I2C has not been correctly executed in the given time
0311  * @VARMLOWSPEEDACCESS_ERR: The command value of VarmLowSpeedVal transfered
0312  *             through I2C has not been correctly executed in the given time
0313  * @VARMRETENTIONVALTO_ERR: The ARM retention supply value transfered through
0314  *                     I2C has not been correctly executed in the given time
0315  * @VARMRETENTIONACCESS_ERR: The command value of VarmRetentionVal transfered
0316  *             through I2C has not been correctly executed in the given time
0317  * @VAPEHIGHSPEEDVALTO_ERR: The APE highspeed supply value transfered through
0318  *                     I2C has not been correctly executed in the given time
0319  * @VSAFEHPVALTO_ERR: The SAFE high power supply value transfered through I2C
0320  *                         has not been correctly executed in the given time
0321  * @VMODSEL1VALTO_ERR: The MODEM sel1 supply value transfered through I2C has
0322  *                             not been correctly executed in the given time
0323  * @VMODSEL2VALTO_ERR: The MODEM sel2 supply value transfered through I2C has
0324  *                             not been correctly executed in the given time
0325  * @VARMOFFACCESS_ERR: The command value of Varm ON/OFF transfered through
0326  *                     I2C has not been correctly executed in the given time
0327  * @VAPEOFFACCESS_ERR: The command value of Vape ON/OFF transfered through
0328  *                     I2C has not been correctly executed in the given time
0329  * @VARMRETACCES_ERR: The command value of Varm retention ON/OFF transfered
0330  *             through I2C has not been correctly executed in the given time
0331  * @CURAPPWRSTISNOTBOOT:Generated when Arm want to do power state transition
0332  *             ApBoot to ApExecute but the power current state is not Apboot
0333  * @CURAPPWRSTISNOTEXECUTE: Generated when Arm want to do power state
0334  *              transition from ApExecute to others power state but the
0335  *              power current state is not ApExecute
0336  * @CURAPPWRSTISNOTSLEEPMODE: Generated when wake up events are transmitted
0337  *             but the power current state is not ApDeepSleep/ApSleep/ApIdle
0338  * @CURAPPWRSTISNOTCORRECTDBG:  Generated when wake up events are transmitted
0339  *              but the power current state is not correct
0340  * @ARMREGU1VALTO_ERR:The ArmRegu1 value transferred through I2C has not
0341  *                    been correctly executed in the given time
0342  * @ARMREGU2VALTO_ERR: The ArmRegu2 value transferred through I2C has not
0343  *                    been correctly executed in the given time
0344  * @VAPEREGUVALTO_ERR: The VApeRegu value transfered through I2C has not
0345  *                    been correctly executed in the given time
0346  * @VSMPS3REGUVALTO_ERR: The VSmps3Regu value transfered through I2C has not
0347  *                      been correctly executed in the given time
0348  * @VMODREGUVALTO_ERR: The VModemRegu value transfered through I2C has not
0349  *                    been correctly executed in the given time
0350  */
0351 enum mbox_to_arm_err {
0352     INIT_ERR = 0x00,
0353     PLLARMLOCKP_ERR = 0x01,
0354     PLLDDRLOCKP_ERR = 0x02,
0355     PLLSOC0LOCKP_ERR = 0x03,
0356     PLLSOC1LOCKP_ERR = 0x04,
0357     ARMWFI_ERR = 0x05,
0358     SYSCLKOK_ERR = 0x06,
0359     BOOT_ERR = 0x07,
0360     ROMCODESAVECONTEXT = 0x08,
0361     VARMHIGHSPEEDVALTO_ERR = 0x10,
0362     VARMHIGHSPEEDACCESS_ERR = 0x11,
0363     VARMLOWSPEEDVALTO_ERR = 0x12,
0364     VARMLOWSPEEDACCESS_ERR = 0x13,
0365     VARMRETENTIONVALTO_ERR = 0x14,
0366     VARMRETENTIONACCESS_ERR = 0x15,
0367     VAPEHIGHSPEEDVALTO_ERR = 0x16,
0368     VSAFEHPVALTO_ERR = 0x17,
0369     VMODSEL1VALTO_ERR = 0x18,
0370     VMODSEL2VALTO_ERR = 0x19,
0371     VARMOFFACCESS_ERR = 0x1A,
0372     VAPEOFFACCESS_ERR = 0x1B,
0373     VARMRETACCES_ERR = 0x1C,
0374     CURAPPWRSTISNOTBOOT = 0x20,
0375     CURAPPWRSTISNOTEXECUTE = 0x21,
0376     CURAPPWRSTISNOTSLEEPMODE = 0x22,
0377     CURAPPWRSTISNOTCORRECTDBG = 0x23,
0378     ARMREGU1VALTO_ERR = 0x24,
0379     ARMREGU2VALTO_ERR = 0x25,
0380     VAPEREGUVALTO_ERR = 0x26,
0381     VSMPS3REGUVALTO_ERR = 0x27,
0382     VMODREGUVALTO_ERR = 0x28
0383 };
0384
0385 enum hw_acc {
0386     SVAMMDSP = 0,
0387     SVAPIPE = 1,
0388     SIAMMDSP = 2,
0389     SIAPIPE = 3,
0390     SGA = 4,
0391     B2R2MCDE = 5,
0392     ESRAM12 = 6,
0393     ESRAM34 = 7,
0394 };
0395
0396 enum cs_pwrmgt {
0397     PWRDNCS0  = 0,
0398     WKUPCS0   = 1,
0399     PWRDNCS1  = 2,
0400     WKUPCS1   = 3
0401 };
0402
0403 /* Defs related to autonomous power management */
0404
0405 /**
0406  * enum sia_sva_pwr_policy - Power policy
0407  * @NO_CHGT:    No change
0408  * @DSPOFF_HWPOFF:
0409  * @DSPOFFRAMRET_HWPOFF:
0410  * @DSPCLKOFF_HWPOFF:
0411  * @DSPCLKOFF_HWPCLKOFF:
0412  *
0413  */
0414 enum sia_sva_pwr_policy {
0415     NO_CHGT         = 0x0,
0416     DSPOFF_HWPOFF       = 0x1,
0417     DSPOFFRAMRET_HWPOFF = 0x2,
0418     DSPCLKOFF_HWPOFF    = 0x3,
0419     DSPCLKOFF_HWPCLKOFF = 0x4,
0420 };
0421
0422 /**
0423  * enum auto_enable - Auto Power enable
0424  * @AUTO_OFF:
0425  * @AUTO_ON:
0426  *
0427  */
0428 enum auto_enable {
0429     AUTO_OFF    = 0x0,
0430     AUTO_ON     = 0x1,
0431 };
0432
0433 /* End of file previously known as prcmu-fw-defs_v1.h */
0434
0435 /**
0436  * enum prcmu_power_status - results from set_power_state
0437  * @PRCMU_SLEEP_OK: Sleep went ok
0438  * @PRCMU_DEEP_SLEEP_OK: DeepSleep went ok
0439  * @PRCMU_IDLE_OK: Idle went ok
0440  * @PRCMU_DEEPIDLE_OK: DeepIdle went ok
0441  * @PRCMU_PRCMU2ARMPENDINGIT_ER: Pending interrupt detected
0442  * @PRCMU_ARMPENDINGIT_ER: Pending interrupt detected
0443  *
0444  */
0445 enum prcmu_power_status {
0446     PRCMU_SLEEP_OK          = 0xf3,
0447     PRCMU_DEEP_SLEEP_OK     = 0xf6,
0448     PRCMU_IDLE_OK           = 0xf0,
0449     PRCMU_DEEPIDLE_OK       = 0xe3,
0450     PRCMU_PRCMU2ARMPENDINGIT_ER = 0x91,
0451     PRCMU_ARMPENDINGIT_ER       = 0x93,
0452 };
0453
0454 /*
0455  * Definitions for autonomous power management configuration.
0456  */
0457
0458 #define PRCMU_AUTO_PM_OFF 0
0459 #define PRCMU_AUTO_PM_ON 1
0460
0461 #define PRCMU_AUTO_PM_POWER_ON_HSEM BIT(0)
0462 #define PRCMU_AUTO_PM_POWER_ON_ABB_FIFO_IT BIT(1)
0463
0464 enum prcmu_auto_pm_policy {
0465     PRCMU_AUTO_PM_POLICY_NO_CHANGE,
0466     PRCMU_AUTO_PM_POLICY_DSP_OFF_HWP_OFF,
0467     PRCMU_AUTO_PM_POLICY_DSP_OFF_RAMRET_HWP_OFF,
0468     PRCMU_AUTO_PM_POLICY_DSP_CLK_OFF_HWP_OFF,
0469     PRCMU_AUTO_PM_POLICY_DSP_CLK_OFF_HWP_CLK_OFF,
0470 };
0471
0472 /**
0473  * struct prcmu_auto_pm_config - Autonomous power management configuration.
0474  * @sia_auto_pm_enable: SIA autonomous pm enable. (PRCMU_AUTO_PM_{OFF,ON})
0475  * @sia_power_on:       SIA power ON enable. (PRCMU_AUTO_PM_POWER_ON_* bitmask)
0476  * @sia_policy:         SIA power policy. (enum prcmu_auto_pm_policy)
0477  * @sva_auto_pm_enable: SVA autonomous pm enable. (PRCMU_AUTO_PM_{OFF,ON})
0478  * @sva_power_on:       SVA power ON enable. (PRCMU_AUTO_PM_POWER_ON_* bitmask)
0479  * @sva_policy:         SVA power policy. (enum prcmu_auto_pm_policy)
0480  */
0481 struct prcmu_auto_pm_config {
0482     u8 sia_auto_pm_enable;
0483     u8 sia_power_on;
0484     u8 sia_policy;
0485     u8 sva_auto_pm_enable;
0486     u8 sva_power_on;
0487     u8 sva_policy;
0488 };
0489
0490 #ifdef CONFIG_MFD_DB8500_PRCMU
0491
0492 void db8500_prcmu_early_init(void);
0493 int prcmu_set_rc_a2p(enum romcode_write);
0494 enum romcode_read prcmu_get_rc_p2a(void);
0495 enum ap_pwrst prcmu_get_xp70_current_state(void);
0496 bool prcmu_has_arm_maxopp(void);
0497 struct prcmu_fw_version *prcmu_get_fw_version(void);
0498 int prcmu_release_usb_wakeup_state(void);
0499 void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep,
0500     struct prcmu_auto_pm_config *idle);
0501 bool prcmu_is_auto_pm_enabled(void);
0502
0503 int prcmu_config_clkout(u8 clkout, u8 source, u8 div);
0504 int prcmu_set_clock_divider(u8 clock, u8 divider);
0505 int db8500_prcmu_config_hotdog(u8 threshold);
0506 int db8500_prcmu_config_hotmon(u8 low, u8 high);
0507 int db8500_prcmu_start_temp_sense(u16 cycles32k);
0508 int db8500_prcmu_stop_temp_sense(void);
0509 int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size);
0510 int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size);
0511
0512 int prcmu_ac_wake_req(void);
0513 void prcmu_ac_sleep_req(void);
0514 void db8500_prcmu_modem_reset(void);
0515
0516 int db8500_prcmu_config_a9wdog(u8 num, bool sleep_auto_off);
0517 int db8500_prcmu_enable_a9wdog(u8 id);
0518 int db8500_prcmu_disable_a9wdog(u8 id);
0519 int db8500_prcmu_kick_a9wdog(u8 id);
0520 int db8500_prcmu_load_a9wdog(u8 id, u32 val);
0521
0522 void db8500_prcmu_system_reset(u16 reset_code);
0523 int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll);
0524 u8 db8500_prcmu_get_power_state_result(void);
0525 void db8500_prcmu_enable_wakeups(u32 wakeups);
0526 int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state);
0527 int db8500_prcmu_request_clock(u8 clock, bool enable);
0528 void db8500_prcmu_config_abb_event_readout(u32 abb_events);
0529 void db8500_prcmu_get_abb_event_buffer(void __iomem **buf);
0530 int db8500_prcmu_config_esram0_deep_sleep(u8 state);
0531 u16 db8500_prcmu_get_reset_code(void);
0532 bool db8500_prcmu_is_ac_wake_requested(void);
0533 int db8500_prcmu_set_arm_opp(u8 opp);
0534 int db8500_prcmu_get_arm_opp(void);
0535 int db8500_prcmu_set_ape_opp(u8 opp);
0536 int db8500_prcmu_get_ape_opp(void);
0537 int db8500_prcmu_request_ape_opp_100_voltage(bool enable);
0538 int db8500_prcmu_get_ddr_opp(void);
0539
0540 u32 db8500_prcmu_read(unsigned int reg);
0541 void db8500_prcmu_write(unsigned int reg, u32 value);
0542 void db8500_prcmu_write_masked(unsigned int reg, u32 mask, u32 value);
0543
0544 #else /* !CONFIG_MFD_DB8500_PRCMU */
0545
0546 static inline void db8500_prcmu_early_init(void) {}
0547
0548 static inline int prcmu_set_rc_a2p(enum romcode_write code)
0549 {
0550     return 0;
0551 }
0552
0553 static inline enum romcode_read prcmu_get_rc_p2a(void)
0554 {
0555     return INIT;
0556 }
0557
0558 static inline enum ap_pwrst prcmu_get_xp70_current_state(void)
0559 {
0560     return AP_EXECUTE;
0561 }
0562
0563 static inline bool prcmu_has_arm_maxopp(void)
0564 {
0565     return false;
0566 }
0567
0568 static inline struct prcmu_fw_version *prcmu_get_fw_version(void)
0569 {
0570     return NULL;
0571 }
0572
0573 static inline int db8500_prcmu_set_ape_opp(u8 opp)
0574 {
0575     return 0;
0576 }
0577
0578 static inline int db8500_prcmu_get_ape_opp(void)
0579 {
0580     return APE_100_OPP;
0581 }
0582
0583 static inline int db8500_prcmu_request_ape_opp_100_voltage(bool enable)
0584 {
0585     return 0;
0586 }
0587
0588 static inline int prcmu_release_usb_wakeup_state(void)
0589 {
0590     return 0;
0591 }
0592
0593 static inline int db8500_prcmu_get_ddr_opp(void)
0594 {
0595     return DDR_100_OPP;
0596 }
0597
0598 static inline void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep,
0599     struct prcmu_auto_pm_config *idle)
0600 {
0601 }
0602
0603 static inline bool prcmu_is_auto_pm_enabled(void)
0604 {
0605     return false;
0606 }
0607
0608 static inline int prcmu_config_clkout(u8 clkout, u8 source, u8 div)
0609 {
0610     return 0;
0611 }
0612
0613 static inline int prcmu_set_clock_divider(u8 clock, u8 divider)
0614 {
0615     return 0;
0616 }
0617
0618 static inline int db8500_prcmu_config_hotdog(u8 threshold)
0619 {
0620     return 0;
0621 }
0622
0623 static inline int db8500_prcmu_config_hotmon(u8 low, u8 high)
0624 {
0625     return 0;
0626 }
0627
0628 static inline int db8500_prcmu_start_temp_sense(u16 cycles32k)
0629 {
0630     return 0;
0631 }
0632
0633 static inline int db8500_prcmu_stop_temp_sense(void)
0634 {
0635     return 0;
0636 }
0637
0638 static inline int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
0639 {
0640     return -ENOSYS;
0641 }
0642
0643 static inline int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
0644 {
0645     return -ENOSYS;
0646 }
0647
0648 static inline int prcmu_ac_wake_req(void)
0649 {
0650     return 0;
0651 }
0652
0653 static inline void prcmu_ac_sleep_req(void) {}
0654
0655 static inline void db8500_prcmu_modem_reset(void) {}
0656
0657 static inline void db8500_prcmu_system_reset(u16 reset_code) {}
0658
0659 static inline int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk,
0660     bool keep_ap_pll)
0661 {
0662     return 0;
0663 }
0664
0665 static inline u8 db8500_prcmu_get_power_state_result(void)
0666 {
0667     return 0;
0668 }
0669
0670 static inline void db8500_prcmu_enable_wakeups(u32 wakeups) {}
0671
0672 static inline int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state)
0673 {
0674     return 0;
0675 }
0676
0677 static inline int db8500_prcmu_request_clock(u8 clock, bool enable)
0678 {
0679     return 0;
0680 }
0681
0682 static inline int db8500_prcmu_config_esram0_deep_sleep(u8 state)
0683 {
0684     return 0;
0685 }
0686
0687 static inline void db8500_prcmu_config_abb_event_readout(u32 abb_events) {}
0688
0689 static inline void db8500_prcmu_get_abb_event_buffer(void __iomem **buf) {}
0690
0691 static inline u16 db8500_prcmu_get_reset_code(void)
0692 {
0693     return 0;
0694 }
0695
0696 static inline int db8500_prcmu_config_a9wdog(u8 num, bool sleep_auto_off)
0697 {
0698     return 0;
0699 }
0700
0701 static inline int db8500_prcmu_enable_a9wdog(u8 id)
0702 {
0703     return 0;
0704 }
0705
0706 static inline int db8500_prcmu_disable_a9wdog(u8 id)
0707 {
0708     return 0;
0709 }
0710
0711 static inline int db8500_prcmu_kick_a9wdog(u8 id)
0712 {
0713     return 0;
0714 }
0715
0716 static inline int db8500_prcmu_load_a9wdog(u8 id, u32 val)
0717 {
0718     return 0;
0719 }
0720
0721 static inline bool db8500_prcmu_is_ac_wake_requested(void)
0722 {
0723     return false;
0724 }
0725
0726 static inline int db8500_prcmu_set_arm_opp(u8 opp)
0727 {
0728     return 0;
0729 }
0730
0731 static inline int db8500_prcmu_get_arm_opp(void)
0732 {
0733     return 0;
0734 }
0735
0736 static inline u32 db8500_prcmu_read(unsigned int reg)
0737 {
0738     return 0;
0739 }
0740
0741 static inline void db8500_prcmu_write(unsigned int reg, u32 value) {}
0742
0743 static inline void db8500_prcmu_write_masked(unsigned int reg, u32 mask,
0744     u32 value) {}
0745
0746 #endif /* !CONFIG_MFD_DB8500_PRCMU */
0747
0748 #endif /* __MFD_DB8500_PRCMU_H */