linux/mfd/davinci_voicecodec.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * DaVinci Voice Codec Core Interface for TI platforms
0004  *
0005  * Copyright (C) 2010 Texas Instruments, Inc
0006  *
0007  * Author: Miguel Aguilar <miguel.aguilar@ridgerun.com>
0008  */
0009
0010 #ifndef __LINUX_MFD_DAVINCI_VOICECODEC_H_
0011 #define __LINUX_MFD_DAVINCI_VOICECODEC_H_
0012
0013 #include <linux/kernel.h>
0014 #include <linux/platform_device.h>
0015 #include <linux/mfd/core.h>
0016 #include <linux/platform_data/edma.h>
0017
0018 struct regmap;
0019
0020 /*
0021  * Register values.
0022  */
0023 #define DAVINCI_VC_PID          0x00
0024 #define DAVINCI_VC_CTRL         0x04
0025 #define DAVINCI_VC_INTEN        0x08
0026 #define DAVINCI_VC_INTSTATUS        0x0c
0027 #define DAVINCI_VC_INTCLR       0x10
0028 #define DAVINCI_VC_EMUL_CTRL        0x14
0029 #define DAVINCI_VC_RFIFO        0x20
0030 #define DAVINCI_VC_WFIFO        0x24
0031 #define DAVINCI_VC_FIFOSTAT     0x28
0032 #define DAVINCI_VC_TST_CTRL     0x2C
0033 #define DAVINCI_VC_REG05        0x94
0034 #define DAVINCI_VC_REG09        0xA4
0035 #define DAVINCI_VC_REG12        0xB0
0036
0037 /* DAVINCI_VC_CTRL bit fields */
0038 #define DAVINCI_VC_CTRL_MASK        0x5500
0039 #define DAVINCI_VC_CTRL_RSTADC      BIT(0)
0040 #define DAVINCI_VC_CTRL_RSTDAC      BIT(1)
0041 #define DAVINCI_VC_CTRL_RD_BITS_8   BIT(4)
0042 #define DAVINCI_VC_CTRL_RD_UNSIGNED BIT(5)
0043 #define DAVINCI_VC_CTRL_WD_BITS_8   BIT(6)
0044 #define DAVINCI_VC_CTRL_WD_UNSIGNED BIT(7)
0045 #define DAVINCI_VC_CTRL_RFIFOEN     BIT(8)
0046 #define DAVINCI_VC_CTRL_RFIFOCL     BIT(9)
0047 #define DAVINCI_VC_CTRL_RFIFOMD_WORD_1  BIT(10)
0048 #define DAVINCI_VC_CTRL_WFIFOEN     BIT(12)
0049 #define DAVINCI_VC_CTRL_WFIFOCL     BIT(13)
0050 #define DAVINCI_VC_CTRL_WFIFOMD_WORD_1  BIT(14)
0051
0052 /* DAVINCI_VC_INT bit fields */
0053 #define DAVINCI_VC_INT_MASK     0x3F
0054 #define DAVINCI_VC_INT_RDRDY_MASK   BIT(0)
0055 #define DAVINCI_VC_INT_RERROVF_MASK BIT(1)
0056 #define DAVINCI_VC_INT_RERRUDR_MASK BIT(2)
0057 #define DAVINCI_VC_INT_WDREQ_MASK   BIT(3)
0058 #define DAVINCI_VC_INT_WERROVF_MASKBIT  BIT(4)
0059 #define DAVINCI_VC_INT_WERRUDR_MASK BIT(5)
0060
0061 /* DAVINCI_VC_REG05 bit fields */
0062 #define DAVINCI_VC_REG05_PGA_GAIN   0x07
0063
0064 /* DAVINCI_VC_REG09 bit fields */
0065 #define DAVINCI_VC_REG09_MUTE       0x40
0066 #define DAVINCI_VC_REG09_DIG_ATTEN  0x3F
0067
0068 /* DAVINCI_VC_REG12 bit fields */
0069 #define DAVINCI_VC_REG12_POWER_ALL_ON   0xFD
0070 #define DAVINCI_VC_REG12_POWER_ALL_OFF  0x00
0071
0072 #define DAVINCI_VC_CELLS        2
0073
0074 enum davinci_vc_cells {
0075     DAVINCI_VC_VCIF_CELL,
0076     DAVINCI_VC_CQ93VC_CELL,
0077 };
0078
0079 struct davinci_vcif {
0080     struct platform_device  *pdev;
0081     u32 dma_tx_channel;
0082     u32 dma_rx_channel;
0083     dma_addr_t dma_tx_addr;
0084     dma_addr_t dma_rx_addr;
0085 };
0086
0087 struct davinci_vc {
0088     /* Device data */
0089     struct device *dev;
0090     struct platform_device *pdev;
0091     struct clk *clk;
0092
0093     /* Memory resources */
0094     void __iomem *base;
0095     struct regmap *regmap;
0096
0097     /* MFD cells */
0098     struct mfd_cell cells[DAVINCI_VC_CELLS];
0099
0100     /* Client devices */
0101     struct davinci_vcif davinci_vcif;
0102 };
0103
0104 #endif