linux/mfd/da8xx-cfgchip.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * TI DaVinci DA8xx CHIPCFGx registers for syscon consumers.
0004  *
0005  * Copyright (C) 2016 David Lechner <david@lechnology.com>
0006  */
0007
0008 #ifndef __LINUX_MFD_DA8XX_CFGCHIP_H
0009 #define __LINUX_MFD_DA8XX_CFGCHIP_H
0010
0011 #include <linux/bitops.h>
0012
0013 /* register offset (32-bit registers) */
0014 #define CFGCHIP(n)              ((n) * 4)
0015
0016 /* CFGCHIP0 (PLL0/EDMA3_0) register bits */
0017 #define CFGCHIP0_PLL_MASTER_LOCK        BIT(4)
0018 #define CFGCHIP0_EDMA30TC1DBS(n)        ((n) << 2)
0019 #define CFGCHIP0_EDMA30TC1DBS_MASK      CFGCHIP0_EDMA30TC1DBS(0x3)
0020 #define CFGCHIP0_EDMA30TC1DBS_16        CFGCHIP0_EDMA30TC1DBS(0x0)
0021 #define CFGCHIP0_EDMA30TC1DBS_32        CFGCHIP0_EDMA30TC1DBS(0x1)
0022 #define CFGCHIP0_EDMA30TC1DBS_64        CFGCHIP0_EDMA30TC1DBS(0x2)
0023 #define CFGCHIP0_EDMA30TC0DBS(n)        ((n) << 0)
0024 #define CFGCHIP0_EDMA30TC0DBS_MASK      CFGCHIP0_EDMA30TC0DBS(0x3)
0025 #define CFGCHIP0_EDMA30TC0DBS_16        CFGCHIP0_EDMA30TC0DBS(0x0)
0026 #define CFGCHIP0_EDMA30TC0DBS_32        CFGCHIP0_EDMA30TC0DBS(0x1)
0027 #define CFGCHIP0_EDMA30TC0DBS_64        CFGCHIP0_EDMA30TC0DBS(0x2)
0028
0029 /* CFGCHIP1 (eCAP/HPI/EDMA3_1/eHRPWM TBCLK/McASP0 AMUTEIN) register bits */
0030 #define CFGCHIP1_CAP2SRC(n)         ((n) << 27)
0031 #define CFGCHIP1_CAP2SRC_MASK           CFGCHIP1_CAP2SRC(0x1f)
0032 #define CFGCHIP1_CAP2SRC_ECAP_PIN       CFGCHIP1_CAP2SRC(0x0)
0033 #define CFGCHIP1_CAP2SRC_MCASP0_TX      CFGCHIP1_CAP2SRC(0x1)
0034 #define CFGCHIP1_CAP2SRC_MCASP0_RX      CFGCHIP1_CAP2SRC(0x2)
0035 #define CFGCHIP1_CAP2SRC_EMAC_C0_RX_THRESHOLD   CFGCHIP1_CAP2SRC(0x7)
0036 #define CFGCHIP1_CAP2SRC_EMAC_C0_RX     CFGCHIP1_CAP2SRC(0x8)
0037 #define CFGCHIP1_CAP2SRC_EMAC_C0_TX     CFGCHIP1_CAP2SRC(0x9)
0038 #define CFGCHIP1_CAP2SRC_EMAC_C0_MISC       CFGCHIP1_CAP2SRC(0xa)
0039 #define CFGCHIP1_CAP2SRC_EMAC_C1_RX_THRESHOLD   CFGCHIP1_CAP2SRC(0xb)
0040 #define CFGCHIP1_CAP2SRC_EMAC_C1_RX     CFGCHIP1_CAP2SRC(0xc)
0041 #define CFGCHIP1_CAP2SRC_EMAC_C1_TX     CFGCHIP1_CAP2SRC(0xd)
0042 #define CFGCHIP1_CAP2SRC_EMAC_C1_MISC       CFGCHIP1_CAP2SRC(0xe)
0043 #define CFGCHIP1_CAP2SRC_EMAC_C2_RX_THRESHOLD   CFGCHIP1_CAP2SRC(0xf)
0044 #define CFGCHIP1_CAP2SRC_EMAC_C2_RX     CFGCHIP1_CAP2SRC(0x10)
0045 #define CFGCHIP1_CAP2SRC_EMAC_C2_TX     CFGCHIP1_CAP2SRC(0x11)
0046 #define CFGCHIP1_CAP2SRC_EMAC_C2_MISC       CFGCHIP1_CAP2SRC(0x12)
0047 #define CFGCHIP1_CAP1SRC(n)         ((n) << 22)
0048 #define CFGCHIP1_CAP1SRC_MASK           CFGCHIP1_CAP1SRC(0x1f)
0049 #define CFGCHIP1_CAP1SRC_ECAP_PIN       CFGCHIP1_CAP1SRC(0x0)
0050 #define CFGCHIP1_CAP1SRC_MCASP0_TX      CFGCHIP1_CAP1SRC(0x1)
0051 #define CFGCHIP1_CAP1SRC_MCASP0_RX      CFGCHIP1_CAP1SRC(0x2)
0052 #define CFGCHIP1_CAP1SRC_EMAC_C0_RX_THRESHOLD   CFGCHIP1_CAP1SRC(0x7)
0053 #define CFGCHIP1_CAP1SRC_EMAC_C0_RX     CFGCHIP1_CAP1SRC(0x8)
0054 #define CFGCHIP1_CAP1SRC_EMAC_C0_TX     CFGCHIP1_CAP1SRC(0x9)
0055 #define CFGCHIP1_CAP1SRC_EMAC_C0_MISC       CFGCHIP1_CAP1SRC(0xa)
0056 #define CFGCHIP1_CAP1SRC_EMAC_C1_RX_THRESHOLD   CFGCHIP1_CAP1SRC(0xb)
0057 #define CFGCHIP1_CAP1SRC_EMAC_C1_RX     CFGCHIP1_CAP1SRC(0xc)
0058 #define CFGCHIP1_CAP1SRC_EMAC_C1_TX     CFGCHIP1_CAP1SRC(0xd)
0059 #define CFGCHIP1_CAP1SRC_EMAC_C1_MISC       CFGCHIP1_CAP1SRC(0xe)
0060 #define CFGCHIP1_CAP1SRC_EMAC_C2_RX_THRESHOLD   CFGCHIP1_CAP1SRC(0xf)
0061 #define CFGCHIP1_CAP1SRC_EMAC_C2_RX     CFGCHIP1_CAP1SRC(0x10)
0062 #define CFGCHIP1_CAP1SRC_EMAC_C2_TX     CFGCHIP1_CAP1SRC(0x11)
0063 #define CFGCHIP1_CAP1SRC_EMAC_C2_MISC       CFGCHIP1_CAP1SRC(0x12)
0064 #define CFGCHIP1_CAP0SRC(n)         ((n) << 17)
0065 #define CFGCHIP1_CAP0SRC_MASK           CFGCHIP1_CAP0SRC(0x1f)
0066 #define CFGCHIP1_CAP0SRC_ECAP_PIN       CFGCHIP1_CAP0SRC(0x0)
0067 #define CFGCHIP1_CAP0SRC_MCASP0_TX      CFGCHIP1_CAP0SRC(0x1)
0068 #define CFGCHIP1_CAP0SRC_MCASP0_RX      CFGCHIP1_CAP0SRC(0x2)
0069 #define CFGCHIP1_CAP0SRC_EMAC_C0_RX_THRESHOLD   CFGCHIP1_CAP0SRC(0x7)
0070 #define CFGCHIP1_CAP0SRC_EMAC_C0_RX     CFGCHIP1_CAP0SRC(0x8)
0071 #define CFGCHIP1_CAP0SRC_EMAC_C0_TX     CFGCHIP1_CAP0SRC(0x9)
0072 #define CFGCHIP1_CAP0SRC_EMAC_C0_MISC       CFGCHIP1_CAP0SRC(0xa)
0073 #define CFGCHIP1_CAP0SRC_EMAC_C1_RX_THRESHOLD   CFGCHIP1_CAP0SRC(0xb)
0074 #define CFGCHIP1_CAP0SRC_EMAC_C1_RX     CFGCHIP1_CAP0SRC(0xc)
0075 #define CFGCHIP1_CAP0SRC_EMAC_C1_TX     CFGCHIP1_CAP0SRC(0xd)
0076 #define CFGCHIP1_CAP0SRC_EMAC_C1_MISC       CFGCHIP1_CAP0SRC(0xe)
0077 #define CFGCHIP1_CAP0SRC_EMAC_C2_RX_THRESHOLD   CFGCHIP1_CAP0SRC(0xf)
0078 #define CFGCHIP1_CAP0SRC_EMAC_C2_RX     CFGCHIP1_CAP0SRC(0x10)
0079 #define CFGCHIP1_CAP0SRC_EMAC_C2_TX     CFGCHIP1_CAP0SRC(0x11)
0080 #define CFGCHIP1_CAP0SRC_EMAC_C2_MISC       CFGCHIP1_CAP0SRC(0x12)
0081 #define CFGCHIP1_HPIBYTEAD          BIT(16)
0082 #define CFGCHIP1_HPIENA             BIT(15)
0083 #define CFGCHIP0_EDMA31TC0DBS(n)        ((n) << 13)
0084 #define CFGCHIP0_EDMA31TC0DBS_MASK      CFGCHIP0_EDMA31TC0DBS(0x3)
0085 #define CFGCHIP0_EDMA31TC0DBS_16        CFGCHIP0_EDMA31TC0DBS(0x0)
0086 #define CFGCHIP0_EDMA31TC0DBS_32        CFGCHIP0_EDMA31TC0DBS(0x1)
0087 #define CFGCHIP0_EDMA31TC0DBS_64        CFGCHIP0_EDMA31TC0DBS(0x2)
0088 #define CFGCHIP1_TBCLKSYNC          BIT(12)
0089 #define CFGCHIP1_AMUTESEL0(n)           ((n) << 0)
0090 #define CFGCHIP1_AMUTESEL0_MASK         CFGCHIP1_AMUTESEL0(0xf)
0091 #define CFGCHIP1_AMUTESEL0_LOW          CFGCHIP1_AMUTESEL0(0x0)
0092 #define CFGCHIP1_AMUTESEL0_BANK_0       CFGCHIP1_AMUTESEL0(0x1)
0093 #define CFGCHIP1_AMUTESEL0_BANK_1       CFGCHIP1_AMUTESEL0(0x2)
0094 #define CFGCHIP1_AMUTESEL0_BANK_2       CFGCHIP1_AMUTESEL0(0x3)
0095 #define CFGCHIP1_AMUTESEL0_BANK_3       CFGCHIP1_AMUTESEL0(0x4)
0096 #define CFGCHIP1_AMUTESEL0_BANK_4       CFGCHIP1_AMUTESEL0(0x5)
0097 #define CFGCHIP1_AMUTESEL0_BANK_5       CFGCHIP1_AMUTESEL0(0x6)
0098 #define CFGCHIP1_AMUTESEL0_BANK_6       CFGCHIP1_AMUTESEL0(0x7)
0099 #define CFGCHIP1_AMUTESEL0_BANK_7       CFGCHIP1_AMUTESEL0(0x8)
0100
0101 /* CFGCHIP2 (USB PHY) register bits */
0102 #define CFGCHIP2_PHYCLKGD           BIT(17)
0103 #define CFGCHIP2_VBUSSENSE          BIT(16)
0104 #define CFGCHIP2_RESET              BIT(15)
0105 #define CFGCHIP2_OTGMODE(n)         ((n) << 13)
0106 #define CFGCHIP2_OTGMODE_MASK           CFGCHIP2_OTGMODE(0x3)
0107 #define CFGCHIP2_OTGMODE_NO_OVERRIDE        CFGCHIP2_OTGMODE(0x0)
0108 #define CFGCHIP2_OTGMODE_FORCE_HOST     CFGCHIP2_OTGMODE(0x1)
0109 #define CFGCHIP2_OTGMODE_FORCE_DEVICE       CFGCHIP2_OTGMODE(0x2)
0110 #define CFGCHIP2_OTGMODE_FORCE_HOST_VBUS_LOW    CFGCHIP2_OTGMODE(0x3)
0111 #define CFGCHIP2_USB1PHYCLKMUX          BIT(12)
0112 #define CFGCHIP2_USB2PHYCLKMUX          BIT(11)
0113 #define CFGCHIP2_PHYPWRDN           BIT(10)
0114 #define CFGCHIP2_OTGPWRDN           BIT(9)
0115 #define CFGCHIP2_DATPOL             BIT(8)
0116 #define CFGCHIP2_USB1SUSPENDM           BIT(7)
0117 #define CFGCHIP2_PHY_PLLON          BIT(6)
0118 #define CFGCHIP2_SESENDEN           BIT(5)
0119 #define CFGCHIP2_VBDTCTEN           BIT(4)
0120 #define CFGCHIP2_REFFREQ(n)         ((n) << 0)
0121 #define CFGCHIP2_REFFREQ_MASK           CFGCHIP2_REFFREQ(0xf)
0122 #define CFGCHIP2_REFFREQ_12MHZ          CFGCHIP2_REFFREQ(0x1)
0123 #define CFGCHIP2_REFFREQ_24MHZ          CFGCHIP2_REFFREQ(0x2)
0124 #define CFGCHIP2_REFFREQ_48MHZ          CFGCHIP2_REFFREQ(0x3)
0125 #define CFGCHIP2_REFFREQ_19_2MHZ        CFGCHIP2_REFFREQ(0x4)
0126 #define CFGCHIP2_REFFREQ_38_4MHZ        CFGCHIP2_REFFREQ(0x5)
0127 #define CFGCHIP2_REFFREQ_13MHZ          CFGCHIP2_REFFREQ(0x6)
0128 #define CFGCHIP2_REFFREQ_26MHZ          CFGCHIP2_REFFREQ(0x7)
0129 #define CFGCHIP2_REFFREQ_20MHZ          CFGCHIP2_REFFREQ(0x8)
0130 #define CFGCHIP2_REFFREQ_40MHZ          CFGCHIP2_REFFREQ(0x9)
0131
0132 /* CFGCHIP3 (EMAC/uPP/PLL1/ASYNC3/PRU/DIV4.5/EMIFA) register bits */
0133 #define CFGCHIP3_RMII_SEL           BIT(8)
0134 #define CFGCHIP3_UPP_TX_CLKSRC          BIT(6)
0135 #define CFGCHIP3_PLL1_MASTER_LOCK       BIT(5)
0136 #define CFGCHIP3_ASYNC3_CLKSRC          BIT(4)
0137 #define CFGCHIP3_PRUEVTSEL          BIT(3)
0138 #define CFGCHIP3_DIV45PENA          BIT(2)
0139 #define CFGCHIP3_EMA_CLKSRC         BIT(1)
0140
0141 /* CFGCHIP4 (McASP0 AMUNTEIN) register bits */
0142 #define CFGCHIP4_AMUTECLR0          BIT(0)
0143
0144 #endif /* __LINUX_MFD_DA8XX_CFGCHIP_H */