linux/mfd/bd9571mwv.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * ROHM BD9571MWV-M and BD9574MWF-M driver
0004  *
0005  * Copyright (C) 2017 Marek Vasut <marek.vasut+renesas@gmail.com>
0006  * Copyright (C) 2020 Renesas Electronics Corporation
0007  *
0008  * Based on the TPS65086 driver
0009  */
0010
0011 #ifndef __LINUX_MFD_BD9571MWV_H
0012 #define __LINUX_MFD_BD9571MWV_H
0013
0014 #include <linux/device.h>
0015 #include <linux/regmap.h>
0016
0017 /* List of registers for BD9571MWV and BD9574MWF */
0018 #define BD9571MWV_VENDOR_CODE           0x00
0019 #define BD9571MWV_VENDOR_CODE_VAL       0xdb
0020 #define BD9571MWV_PRODUCT_CODE          0x01
0021 #define BD9571MWV_PRODUCT_CODE_BD9571MWV    0x60
0022 #define BD9571MWV_PRODUCT_CODE_BD9574MWF    0x74
0023 #define BD9571MWV_PRODUCT_REVISION      0x02
0024
0025 #define BD9571MWV_I2C_FUSA_MODE         0x10
0026 #define BD9571MWV_I2C_MD2_E1_BIT_1      0x11
0027 #define BD9571MWV_I2C_MD2_E1_BIT_2      0x12
0028
0029 #define BD9571MWV_BKUP_MODE_CNT         0x20
0030 #define BD9571MWV_BKUP_MODE_CNT_KEEPON_MASK GENMASK(3, 0)
0031 #define BD9571MWV_BKUP_MODE_CNT_KEEPON_DDR0 BIT(0)
0032 #define BD9571MWV_BKUP_MODE_CNT_KEEPON_DDR1 BIT(1)
0033 #define BD9571MWV_BKUP_MODE_CNT_KEEPON_DDR0C    BIT(2)
0034 #define BD9571MWV_BKUP_MODE_CNT_KEEPON_DDR1C    BIT(3)
0035 #define BD9571MWV_BKUP_MODE_STATUS      0x21
0036 #define BD9571MWV_BKUP_RECOVERY_CNT     0x22
0037 #define BD9571MWV_BKUP_CTRL_TIM_CNT     0x23
0038 #define BD9571MWV_WAITBKUP_WDT_CNT      0x24
0039 #define BD9571MWV_128H_TIM_CNT          0x26
0040 #define BD9571MWV_QLLM_CNT          0x27
0041
0042 #define BD9571MWV_AVS_SET_MONI          0x31
0043 #define BD9571MWV_AVS_SET_MONI_MASK     0x3
0044 #define BD9571MWV_AVS_VD09_VID(n)       (0x32 + (n))
0045 #define BD9571MWV_AVS_DVFS_VID(n)       (0x36 + (n))
0046
0047 #define BD9571MWV_VD18_VID          0x42
0048 #define BD9571MWV_VD25_VID          0x43
0049 #define BD9571MWV_VD33_VID          0x44
0050
0051 #define BD9571MWV_DVFS_VINIT            0x50
0052 #define BD9574MWF_VD09_VINIT            0x51
0053 #define BD9571MWV_DVFS_SETVMAX          0x52
0054 #define BD9571MWV_DVFS_BOOSTVID         0x53
0055 #define BD9571MWV_DVFS_SETVID           0x54
0056 #define BD9571MWV_DVFS_MONIVDAC         0x55
0057 #define BD9571MWV_DVFS_PGD_CNT          0x56
0058
0059 #define BD9571MWV_GPIO_DIR          0x60
0060 #define BD9571MWV_GPIO_OUT          0x61
0061 #define BD9571MWV_GPIO_IN           0x62
0062 #define BD9571MWV_GPIO_DEB          0x63
0063 #define BD9571MWV_GPIO_INT_SET          0x64
0064 #define BD9571MWV_GPIO_INT          0x65
0065 #define BD9571MWV_GPIO_INTMASK          0x66
0066 #define BD9574MWF_GPIO_MUX          0x67
0067
0068 #define BD9571MWV_REG_KEEP(n)           (0x70 + (n))
0069
0070 #define BD9571MWV_PMIC_INTERNAL_STATUS      0x80
0071 #define BD9571MWV_PROT_ERROR_STATUS0        0x81
0072 #define BD9571MWV_PROT_ERROR_STATUS1        0x82
0073 #define BD9571MWV_PROT_ERROR_STATUS2        0x83
0074 #define BD9571MWV_PROT_ERROR_STATUS3        0x84
0075 #define BD9571MWV_PROT_ERROR_STATUS4        0x85
0076 #define BD9574MWF_PROT_ERROR_STATUS5        0x86
0077 #define BD9574MWF_SYSTEM_ERROR_STATUS       0x87
0078
0079 #define BD9571MWV_INT_INTREQ            0x90
0080 #define BD9571MWV_INT_INTREQ_MD1_INT        BIT(0)
0081 #define BD9571MWV_INT_INTREQ_MD2_E1_INT     BIT(1)
0082 #define BD9571MWV_INT_INTREQ_MD2_E2_INT     BIT(2)
0083 #define BD9571MWV_INT_INTREQ_PROT_ERR_INT   BIT(3)
0084 #define BD9571MWV_INT_INTREQ_GP_INT     BIT(4)
0085 #define BD9571MWV_INT_INTREQ_128H_OF_INT    BIT(5)
0086 #define BD9571MWV_INT_INTREQ_WDT_OF_INT     BIT(6)
0087 #define BD9571MWV_INT_INTREQ_BKUP_TRG_INT   BIT(7)
0088 #define BD9571MWV_INT_INTMASK           0x91
0089
0090 #define BD9574MWF_SSCG_CNT          0xA0
0091 #define BD9574MWF_POFFB_MRB         0xA1
0092 #define BD9574MWF_SMRB_WR_PROT          0xA2
0093 #define BD9574MWF_SMRB_ASSERT           0xA3
0094 #define BD9574MWF_SMRB_STATUS           0xA4
0095
0096 #define BD9571MWV_ACCESS_KEY            0xff
0097
0098 /* Define the BD9571MWV IRQ numbers */
0099 enum bd9571mwv_irqs {
0100     BD9571MWV_IRQ_MD1,
0101     BD9571MWV_IRQ_MD2_E1,
0102     BD9571MWV_IRQ_MD2_E2,
0103     BD9571MWV_IRQ_PROT_ERR,
0104     BD9571MWV_IRQ_GP,
0105     BD9571MWV_IRQ_128H_OF,  /* BKUP_HOLD on BD9574MWF */
0106     BD9571MWV_IRQ_WDT_OF,
0107     BD9571MWV_IRQ_BKUP_TRG,
0108 };
0109 #endif /* __LINUX_MFD_BD9571MWV_H */