linux/mfd/asic3.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * include/linux/mfd/asic3.h
0004  *
0005  * Compaq ASIC3 headers.
0006  *
0007  * Copyright 2001 Compaq Computer Corporation.
0008  * Copyright 2007-2008 OpenedHand Ltd.
0009  */
0010
0011 #ifndef __ASIC3_H__
0012 #define __ASIC3_H__
0013
0014 #include <linux/types.h>
0015
0016 struct led_classdev;
0017 struct asic3_led {
0018     const char  *name;
0019     const char  *default_trigger;
0020     struct led_classdev *cdev;
0021 };
0022
0023 struct asic3_platform_data {
0024     u16 *gpio_config;
0025     unsigned int gpio_config_num;
0026
0027     unsigned int irq_base;
0028
0029     unsigned int gpio_base;
0030
0031     unsigned int clock_rate;
0032
0033     struct asic3_led *leds;
0034 };
0035
0036 #define ASIC3_NUM_GPIO_BANKS    4
0037 #define ASIC3_GPIOS_PER_BANK    16
0038 #define ASIC3_NUM_GPIOS     64
0039 #define ASIC3_NR_IRQS       ASIC3_NUM_GPIOS + 6
0040
0041 #define ASIC3_IRQ_LED0      64
0042 #define ASIC3_IRQ_LED1      65
0043 #define ASIC3_IRQ_LED2      66
0044 #define ASIC3_IRQ_SPI       67
0045 #define ASIC3_IRQ_SMBUS     68
0046 #define ASIC3_IRQ_OWM       69
0047
0048 #define ASIC3_TO_GPIO(gpio) (NR_BUILTIN_GPIO + (gpio))
0049
0050 #define ASIC3_GPIO_BANK_A   0
0051 #define ASIC3_GPIO_BANK_B   1
0052 #define ASIC3_GPIO_BANK_C   2
0053 #define ASIC3_GPIO_BANK_D   3
0054
0055 #define ASIC3_GPIO(bank, gpio) \
0056     ((ASIC3_GPIOS_PER_BANK * ASIC3_GPIO_BANK_##bank) + (gpio))
0057 #define ASIC3_GPIO_bit(gpio) (1 << (gpio & 0xf))
0058 /* All offsets below are specified with this address bus shift */
0059 #define ASIC3_DEFAULT_ADDR_SHIFT 2
0060
0061 #define ASIC3_OFFSET(base, reg) (ASIC3_##base##_BASE + ASIC3_##base##_##reg)
0062 #define ASIC3_GPIO_OFFSET(base, reg) \
0063     (ASIC3_GPIO_##base##_BASE + ASIC3_GPIO_##reg)
0064
0065 #define ASIC3_GPIO_A_BASE      0x0000
0066 #define ASIC3_GPIO_B_BASE      0x0100
0067 #define ASIC3_GPIO_C_BASE      0x0200
0068 #define ASIC3_GPIO_D_BASE      0x0300
0069
0070 #define ASIC3_GPIO_TO_BANK(gpio) ((gpio) >> 4)
0071 #define ASIC3_GPIO_TO_BIT(gpio)  ((gpio) - \
0072                   (ASIC3_GPIOS_PER_BANK * ((gpio) >> 4)))
0073 #define ASIC3_GPIO_TO_MASK(gpio) (1 << ASIC3_GPIO_TO_BIT(gpio))
0074 #define ASIC3_GPIO_TO_BASE(gpio) (ASIC3_GPIO_A_BASE + (((gpio) >> 4) * 0x0100))
0075 #define ASIC3_BANK_TO_BASE(bank) (ASIC3_GPIO_A_BASE + ((bank) * 0x100))
0076
0077 #define ASIC3_GPIO_MASK          0x00    /* R/W 0:don't mask */
0078 #define ASIC3_GPIO_DIRECTION     0x04    /* R/W 0:input */
0079 #define ASIC3_GPIO_OUT           0x08    /* R/W 0:output low */
0080 #define ASIC3_GPIO_TRIGGER_TYPE  0x0c    /* R/W 0:level */
0081 #define ASIC3_GPIO_EDGE_TRIGGER  0x10    /* R/W 0:falling */
0082 #define ASIC3_GPIO_LEVEL_TRIGGER 0x14    /* R/W 0:low level detect */
0083 #define ASIC3_GPIO_SLEEP_MASK    0x18    /* R/W 0:don't mask in sleep mode */
0084 #define ASIC3_GPIO_SLEEP_OUT     0x1c    /* R/W level 0:low in sleep mode */
0085 #define ASIC3_GPIO_BAT_FAULT_OUT 0x20    /* R/W level 0:low in batt_fault */
0086 #define ASIC3_GPIO_INT_STATUS    0x24    /* R/W 0:none, 1:detect */
0087 #define ASIC3_GPIO_ALT_FUNCTION  0x28    /* R/W 1:LED register control */
0088 #define ASIC3_GPIO_SLEEP_CONF    0x2c    /*
0089                       * R/W bit 1: autosleep
0090                       * 0: disable gposlpout in normal mode,
0091                       * enable gposlpout in sleep mode.
0092                       */
0093 #define ASIC3_GPIO_STATUS        0x30    /* R   Pin status */
0094
0095 /*
0096  * ASIC3 GPIO config
0097  *
0098  * Bits 0..6   gpio number
0099  * Bits 7..13  Alternate function
0100  * Bit  14     Direction
0101  * Bit  15     Initial value
0102  *
0103  */
0104 #define ASIC3_CONFIG_GPIO_PIN(config) ((config) & 0x7f)
0105 #define ASIC3_CONFIG_GPIO_ALT(config)  (((config) & (0x7f << 7)) >> 7)
0106 #define ASIC3_CONFIG_GPIO_DIR(config)  ((config & (1 << 14)) >> 14)
0107 #define ASIC3_CONFIG_GPIO_INIT(config) ((config & (1 << 15)) >> 15)
0108 #define ASIC3_CONFIG_GPIO(gpio, alt, dir, init) (((gpio) & 0x7f) \
0109     | (((alt) & 0x7f) << 7) | (((dir) & 0x1) << 14) \
0110     | (((init) & 0x1) << 15))
0111 #define ASIC3_CONFIG_GPIO_DEFAULT(gpio, dir, init) \
0112     ASIC3_CONFIG_GPIO((gpio), 0, (dir), (init))
0113 #define ASIC3_CONFIG_GPIO_DEFAULT_OUT(gpio, init) \
0114     ASIC3_CONFIG_GPIO((gpio), 0, 1, (init))
0115
0116 /*
0117  * Alternate functions
0118  */
0119 #define ASIC3_GPIOA11_PWM0      ASIC3_CONFIG_GPIO(11, 1, 1, 0)
0120 #define ASIC3_GPIOA12_PWM1      ASIC3_CONFIG_GPIO(12, 1, 1, 0)
0121 #define ASIC3_GPIOA15_CONTROL_CX    ASIC3_CONFIG_GPIO(15, 1, 1, 0)
0122 #define ASIC3_GPIOC0_LED0       ASIC3_CONFIG_GPIO(32, 1, 0, 0)
0123 #define ASIC3_GPIOC1_LED1       ASIC3_CONFIG_GPIO(33, 1, 0, 0)
0124 #define ASIC3_GPIOC2_LED2       ASIC3_CONFIG_GPIO(34, 1, 0, 0)
0125 #define ASIC3_GPIOC3_SPI_RXD        ASIC3_CONFIG_GPIO(35, 1, 0, 0)
0126 #define ASIC3_GPIOC4_CF_nCD     ASIC3_CONFIG_GPIO(36, 1, 0, 0)
0127 #define ASIC3_GPIOC4_SPI_TXD        ASIC3_CONFIG_GPIO(36, 1, 1, 0)
0128 #define ASIC3_GPIOC5_SPI_CLK        ASIC3_CONFIG_GPIO(37, 1, 1, 0)
0129 #define ASIC3_GPIOC5_nCIOW      ASIC3_CONFIG_GPIO(37, 1, 1, 0)
0130 #define ASIC3_GPIOC6_nCIOR      ASIC3_CONFIG_GPIO(38, 1, 1, 0)
0131 #define ASIC3_GPIOC7_nPCE_1     ASIC3_CONFIG_GPIO(39, 1, 0, 0)
0132 #define ASIC3_GPIOC8_nPCE_2     ASIC3_CONFIG_GPIO(40, 1, 0, 0)
0133 #define ASIC3_GPIOC9_nPOE       ASIC3_CONFIG_GPIO(41, 1, 0, 0)
0134 #define ASIC3_GPIOC10_nPWE      ASIC3_CONFIG_GPIO(42, 1, 0, 0)
0135 #define ASIC3_GPIOC11_PSKTSEL       ASIC3_CONFIG_GPIO(43, 1, 0, 0)
0136 #define ASIC3_GPIOC12_nPREG     ASIC3_CONFIG_GPIO(44, 1, 0, 0)
0137 #define ASIC3_GPIOC13_nPWAIT        ASIC3_CONFIG_GPIO(45, 1, 1, 0)
0138 #define ASIC3_GPIOC14_nPIOIS16      ASIC3_CONFIG_GPIO(46, 1, 1, 0)
0139 #define ASIC3_GPIOC15_nPIOR     ASIC3_CONFIG_GPIO(47, 1, 0, 0)
0140 #define ASIC3_GPIOD4_CF_nCD     ASIC3_CONFIG_GPIO(52, 1, 0, 0)
0141 #define ASIC3_GPIOD11_nCIOIS16      ASIC3_CONFIG_GPIO(59, 1, 0, 0)
0142 #define ASIC3_GPIOD12_nCWAIT        ASIC3_CONFIG_GPIO(60, 1, 0, 0)
0143 #define ASIC3_GPIOD15_nPIOW     ASIC3_CONFIG_GPIO(63, 1, 0, 0)
0144
0145
0146 #define ASIC3_SPI_Base            0x0400
0147 #define ASIC3_SPI_Control               0x0000
0148 #define ASIC3_SPI_TxData                0x0004
0149 #define ASIC3_SPI_RxData                0x0008
0150 #define ASIC3_SPI_Int                   0x000c
0151 #define ASIC3_SPI_Status                0x0010
0152
0153 #define SPI_CONTROL_SPR(clk)      ((clk) & 0x0f)  /* Clock rate */
0154
0155 #define ASIC3_PWM_0_Base                0x0500
0156 #define ASIC3_PWM_1_Base                0x0600
0157 #define ASIC3_PWM_TimeBase              0x0000
0158 #define ASIC3_PWM_PeriodTime            0x0004
0159 #define ASIC3_PWM_DutyTime              0x0008
0160
0161 #define PWM_TIMEBASE_VALUE(x)    ((x)&0xf)   /* Low 4 bits sets time base */
0162 #define PWM_TIMEBASE_ENABLE     (1 << 4)   /* Enable clock */
0163
0164 #define ASIC3_NUM_LEDS                  3
0165 #define ASIC3_LED_0_Base                0x0700
0166 #define ASIC3_LED_1_Base                0x0800
0167 #define ASIC3_LED_2_Base              0x0900
0168 #define ASIC3_LED_TimeBase              0x0000    /* R/W  7 bits */
0169 #define ASIC3_LED_PeriodTime            0x0004    /* R/W 12 bits */
0170 #define ASIC3_LED_DutyTime              0x0008    /* R/W 12 bits */
0171 #define ASIC3_LED_AutoStopCount         0x000c    /* R/W 16 bits */
0172
0173 /* LED TimeBase bits - match ASIC2 */
0174 #define LED_TBS     0x0f /* Low 4 bits sets time base, max = 13 */
0175                  /* Note: max = 5 on hx4700 */
0176                  /* 0: maximum time base */
0177                  /* 1: maximum time base / 2 */
0178                  /* n: maximum time base / 2^n */
0179
0180 #define LED_EN      (1 << 4) /* LED ON/OFF 0:off, 1:on */
0181 #define LED_AUTOSTOP    (1 << 5) /* LED ON/OFF auto stop 0:disable, 1:enable */
0182 #define LED_ALWAYS  (1 << 6) /* LED Interrupt Mask 0:No mask, 1:mask */
0183
0184 #define ASIC3_CLOCK_BASE       0x0A00
0185 #define ASIC3_CLOCK_CDEX           0x00
0186 #define ASIC3_CLOCK_SEL            0x04
0187
0188 #define CLOCK_CDEX_SOURCE       (1 << 0)  /* 2 bits */
0189 #define CLOCK_CDEX_SOURCE0      (1 << 0)
0190 #define CLOCK_CDEX_SOURCE1      (1 << 1)
0191 #define CLOCK_CDEX_SPI          (1 << 2)
0192 #define CLOCK_CDEX_OWM          (1 << 3)
0193 #define CLOCK_CDEX_PWM0         (1 << 4)
0194 #define CLOCK_CDEX_PWM1         (1 << 5)
0195 #define CLOCK_CDEX_LED0         (1 << 6)
0196 #define CLOCK_CDEX_LED1         (1 << 7)
0197 #define CLOCK_CDEX_LED2         (1 << 8)
0198
0199 /* Clocks settings: 1 for 24.576 MHz, 0 for 12.288Mhz */
0200 #define CLOCK_CDEX_SD_HOST      (1 << 9)   /* R/W: SD host clock source */
0201 #define CLOCK_CDEX_SD_BUS       (1 << 10)  /* R/W: SD bus clock source ctrl */
0202 #define CLOCK_CDEX_SMBUS        (1 << 11)
0203 #define CLOCK_CDEX_CONTROL_CX   (1 << 12)
0204
0205 #define CLOCK_CDEX_EX0          (1 << 13)  /* R/W: 32.768 kHz crystal */
0206 #define CLOCK_CDEX_EX1          (1 << 14)  /* R/W: 24.576 MHz crystal */
0207
0208 #define CLOCK_SEL_SD_HCLK_SEL   (1 << 0)   /* R/W: SDIO host clock select */
0209 #define CLOCK_SEL_SD_BCLK_SEL   (1 << 1)   /* R/W: SDIO bus clock select */
0210
0211 /* R/W: INT clock source control (32.768 kHz) */
0212 #define CLOCK_SEL_CX            (1 << 2)
0213
0214
0215 #define ASIC3_INTR_BASE     0x0B00
0216
0217 #define ASIC3_INTR_INT_MASK       0x00  /* Interrupt mask control */
0218 #define ASIC3_INTR_P_INT_STAT     0x04  /* Peripheral interrupt status */
0219 #define ASIC3_INTR_INT_CPS        0x08  /* Interrupt timer clock pre-scale */
0220 #define ASIC3_INTR_INT_TBS        0x0c  /* Interrupt timer set */
0221
0222 #define ASIC3_INTMASK_GINTMASK    (1 << 0)  /* Global INTs mask 1:enable */
0223 #define ASIC3_INTMASK_GINTEL      (1 << 1)  /* 1: rising edge, 0: hi level */
0224 #define ASIC3_INTMASK_MASK0       (1 << 2)
0225 #define ASIC3_INTMASK_MASK1       (1 << 3)
0226 #define ASIC3_INTMASK_MASK2       (1 << 4)
0227 #define ASIC3_INTMASK_MASK3       (1 << 5)
0228 #define ASIC3_INTMASK_MASK4       (1 << 6)
0229 #define ASIC3_INTMASK_MASK5       (1 << 7)
0230
0231 #define ASIC3_INTR_PERIPHERAL_A   (1 << 0)
0232 #define ASIC3_INTR_PERIPHERAL_B   (1 << 1)
0233 #define ASIC3_INTR_PERIPHERAL_C   (1 << 2)
0234 #define ASIC3_INTR_PERIPHERAL_D   (1 << 3)
0235 #define ASIC3_INTR_LED0           (1 << 4)
0236 #define ASIC3_INTR_LED1           (1 << 5)
0237 #define ASIC3_INTR_LED2           (1 << 6)
0238 #define ASIC3_INTR_SPI            (1 << 7)
0239 #define ASIC3_INTR_SMBUS          (1 << 8)
0240 #define ASIC3_INTR_OWM            (1 << 9)
0241
0242 #define ASIC3_INTR_CPS(x)         ((x)&0x0f)    /* 4 bits, max 14 */
0243 #define ASIC3_INTR_CPS_SET        (1 << 4)    /* Time base enable */
0244
0245
0246 /* Basic control of the SD ASIC */
0247 #define ASIC3_SDHWCTRL_BASE     0x0E00
0248 #define ASIC3_SDHWCTRL_SDCONF     0x00
0249
0250 #define ASIC3_SDHWCTRL_SUSPEND    (1 << 0)  /* 1=suspend all SD operations */
0251 #define ASIC3_SDHWCTRL_CLKSEL     (1 << 1)  /* 1=SDICK, 0=HCLK */
0252 #define ASIC3_SDHWCTRL_PCLR       (1 << 2)  /* All registers of SDIO cleared */
0253 #define ASIC3_SDHWCTRL_LEVCD      (1 << 3)  /* SD card detection: 0:low */
0254
0255 /* SD card write protection: 0=high */
0256 #define ASIC3_SDHWCTRL_LEVWP      (1 << 4)
0257 #define ASIC3_SDHWCTRL_SDLED      (1 << 5)  /* SD card LED signal 0=disable */
0258
0259 /* SD card power supply ctrl 1=enable */
0260 #define ASIC3_SDHWCTRL_SDPWR      (1 << 6)
0261
0262 #define ASIC3_EXTCF_BASE        0x1100
0263
0264 #define ASIC3_EXTCF_SELECT        0x00
0265 #define ASIC3_EXTCF_RESET         0x04
0266
0267 #define ASIC3_EXTCF_SMOD0            (1 << 0)  /* slot number of mode 0 */
0268 #define ASIC3_EXTCF_SMOD1            (1 << 1)  /* slot number of mode 1 */
0269 #define ASIC3_EXTCF_SMOD2            (1 << 2)  /* slot number of mode 2 */
0270 #define ASIC3_EXTCF_OWM_EN           (1 << 4)  /* enable onewire module */
0271 #define ASIC3_EXTCF_OWM_SMB          (1 << 5)  /* OWM bus selection */
0272 #define ASIC3_EXTCF_OWM_RESET            (1 << 6)  /* ?? used by OWM and CF */
0273 #define ASIC3_EXTCF_CF0_SLEEP_MODE       (1 << 7)  /* CF0 sleep state */
0274 #define ASIC3_EXTCF_CF1_SLEEP_MODE       (1 << 8)  /* CF1 sleep state */
0275 #define ASIC3_EXTCF_CF0_PWAIT_EN         (1 << 10) /* CF0 PWAIT_n control */
0276 #define ASIC3_EXTCF_CF1_PWAIT_EN         (1 << 11) /* CF1 PWAIT_n control */
0277 #define ASIC3_EXTCF_CF0_BUF_EN           (1 << 12) /* CF0 buffer control */
0278 #define ASIC3_EXTCF_CF1_BUF_EN           (1 << 13) /* CF1 buffer control */
0279 #define ASIC3_EXTCF_SD_MEM_ENABLE        (1 << 14)
0280 #define ASIC3_EXTCF_CF_SLEEP             (1 << 15) /* CF sleep mode control */
0281
0282 /*********************************************
0283  *  The Onewire interface (DS1WM) is handled
0284  *  by the ds1wm driver.
0285  *
0286  *********************************************/
0287
0288 #define ASIC3_OWM_BASE      0xC00
0289
0290 /*****************************************************************************
0291  *  The SD configuration registers are at a completely different location
0292  *  in memory.  They are divided into three sets of registers:
0293  *
0294  *  SD_CONFIG         Core configuration register
0295  *  SD_CTRL           Control registers for SD operations
0296  *  SDIO_CTRL         Control registers for SDIO operations
0297  *
0298  *****************************************************************************/
0299 #define ASIC3_SD_CONFIG_BASE    0x0400 /* Assumes 32 bit addressing */
0300 #define ASIC3_SD_CONFIG_SIZE    0x0200 /* Assumes 32 bit addressing */
0301 #define ASIC3_SD_CTRL_BASE  0x1000
0302 #define ASIC3_SDIO_CTRL_BASE    0x1200
0303
0304 #define ASIC3_MAP_SIZE_32BIT    0x2000
0305 #define ASIC3_MAP_SIZE_16BIT    0x1000
0306
0307 /* Functions needed by leds-asic3 */
0308
0309 struct asic3;
0310 extern void asic3_write_register(struct asic3 *asic, unsigned int reg, u32 val);
0311 extern u32 asic3_read_register(struct asic3 *asic, unsigned int reg);
0312
0313 #endif /* __ASIC3_H__ */