linux/mfd/altera-a10sr.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright Intel Corporation (C) 2014-2016. All Rights Reserved
0004  *
0005  * Declarations for Altera Arria10 MAX5 System Resource Chip
0006  *
0007  * Adapted from DA9052
0008  */
0009
0010 #ifndef __MFD_ALTERA_A10SR_H
0011 #define __MFD_ALTERA_A10SR_H
0012
0013 #include <linux/completion.h>
0014 #include <linux/list.h>
0015 #include <linux/mfd/core.h>
0016 #include <linux/regmap.h>
0017 #include <linux/slab.h>
0018
0019 /* Write registers are always on even addresses */
0020 #define  WRITE_REG_MASK              0xFE
0021 /* Odd registers are always on odd addresses */
0022 #define  READ_REG_MASK               0x01
0023
0024 #define ALTR_A10SR_BITS_PER_REGISTER  8
0025 /*
0026  * To find the correct register, we divide the input GPIO by
0027  * the number of GPIO in each register. We then need to multiply
0028  * by 2 because the reads are at odd addresses.
0029  */
0030 #define ALTR_A10SR_REG_OFFSET(X)     (((X) / ALTR_A10SR_BITS_PER_REGISTER) << 1)
0031 #define ALTR_A10SR_REG_BIT(X)        ((X) % ALTR_A10SR_BITS_PER_REGISTER)
0032 #define ALTR_A10SR_REG_BIT_CHG(X, Y) ((X) << ALTR_A10SR_REG_BIT(Y))
0033 #define ALTR_A10SR_REG_BIT_MASK(X)   (1 << ALTR_A10SR_REG_BIT(X))
0034
0035 /* Arria10 System Controller Register Defines */
0036 #define ALTR_A10SR_NOP                0x00    /* No Change */
0037 #define ALTR_A10SR_VERSION_READ       0x00    /* MAX5 Version Read */
0038
0039 #define ALTR_A10SR_LED_REG            0x02    /* LED - Upper 4 bits */
0040 /* LED register Bit Definitions */
0041 #define ALTR_A10SR_LED_VALID_SHIFT        4       /* LED - Upper 4 bits valid */
0042 #define ALTR_A10SR_OUT_VALID_RANGE_LO     ALTR_A10SR_LED_VALID_SHIFT
0043 #define ALTR_A10SR_OUT_VALID_RANGE_HI     7
0044
0045 #define ALTR_A10SR_PBDSW_REG          0x04    /* PB & DIP SW - Input only */
0046 #define ALTR_A10SR_PBDSW_IRQ_REG      0x06    /* PB & DIP SW Flag Clear */
0047 /* Pushbutton & DIP Switch Bit Definitions */
0048 #define ALTR_A10SR_IN_VALID_RANGE_LO      8
0049 #define ALTR_A10SR_IN_VALID_RANGE_HI      15
0050
0051 #define ALTR_A10SR_PWR_GOOD1_REG      0x08    /* Power Good1 Read */
0052 #define ALTR_A10SR_PWR_GOOD2_REG      0x0A    /* Power Good2 Read */
0053 #define ALTR_A10SR_PWR_GOOD3_REG      0x0C    /* Power Good3 Read */
0054 #define ALTR_A10SR_FMCAB_REG          0x0E    /* FMCA/B & PCIe Pwr Enable */
0055 #define ALTR_A10SR_HPS_RST_REG        0x10    /* HPS Reset */
0056 #define ALTR_A10SR_USB_QSPI_REG       0x12    /* USB, BQSPI, FILE Reset */
0057 #define ALTR_A10SR_SFPA_REG           0x14    /* SFPA Control Reg */
0058 #define ALTR_A10SR_SFPB_REG           0x16    /* SFPB Control Reg */
0059 #define ALTR_A10SR_I2C_M_REG          0x18    /* I2C Master Select */
0060 #define ALTR_A10SR_WARM_RST_REG       0x1A    /* HPS Warm Reset */
0061 #define ALTR_A10SR_WR_KEY_REG         0x1C    /* HPS Warm Reset Key */
0062 #define ALTR_A10SR_PMBUS_REG          0x1E    /* HPS PM Bus */
0063
0064 /**
0065  * struct altr_a10sr - Altera Max5 MFD device private data structure
0066  * @dev:  : this device
0067  * @regmap: the regmap assigned to the parent device.
0068  */
0069 struct altr_a10sr {
0070     struct device *dev;
0071     struct regmap *regmap;
0072 };
0073
0074 #endif /* __MFD_ALTERA_A10SR_H */