linux/mdio/mdio-xgene.h

0001 /* SPDX-License-Identifier: GPL-2.0+ */
0002 /* Applied Micro X-Gene SoC MDIO Driver
0003  *
0004  * Copyright (c) 2016, Applied Micro Circuits Corporation
0005  * Author: Iyappan Subramanian <isubramanian@apm.com>
0006  */
0007
0008 #ifndef __MDIO_XGENE_H__
0009 #define __MDIO_XGENE_H__
0010
0011 #include <linux/bits.h>
0012 #include <linux/spinlock.h>
0013 #include <linux/types.h>
0014
0015 #define BLOCK_XG_MDIO_CSR_OFFSET    0x5000
0016 #define BLOCK_DIAG_CSR_OFFSET       0xd000
0017 #define XGENET_CONFIG_REG_ADDR      0x20
0018
0019 #define MAC_ADDR_REG_OFFSET     0x00
0020 #define MAC_COMMAND_REG_OFFSET      0x04
0021 #define MAC_WRITE_REG_OFFSET        0x08
0022 #define MAC_READ_REG_OFFSET     0x0c
0023 #define MAC_COMMAND_DONE_REG_OFFSET 0x10
0024
0025 #define CLKEN_OFFSET            0x08
0026 #define SRST_OFFSET         0x00
0027
0028 #define MENET_CFG_MEM_RAM_SHUTDOWN_ADDR 0x70
0029 #define MENET_BLOCK_MEM_RDY_ADDR    0x74
0030
0031 #define MAC_CONFIG_1_ADDR       0x00
0032 #define MII_MGMT_COMMAND_ADDR       0x24
0033 #define MII_MGMT_ADDRESS_ADDR       0x28
0034 #define MII_MGMT_CONTROL_ADDR       0x2c
0035 #define MII_MGMT_STATUS_ADDR        0x30
0036 #define MII_MGMT_INDICATORS_ADDR    0x34
0037 #define SOFT_RESET          BIT(31)
0038
0039 #define MII_MGMT_CONFIG_ADDR            0x20
0040 #define MII_MGMT_COMMAND_ADDR           0x24
0041 #define MII_MGMT_ADDRESS_ADDR           0x28
0042 #define MII_MGMT_CONTROL_ADDR           0x2c
0043 #define MII_MGMT_STATUS_ADDR            0x30
0044 #define MII_MGMT_INDICATORS_ADDR        0x34
0045
0046 #define MIIM_COMMAND_ADDR               0x20
0047 #define MIIM_FIELD_ADDR                 0x24
0048 #define MIIM_CONFIGURATION_ADDR         0x28
0049 #define MIIM_LINKFAILVECTOR_ADDR        0x2c
0050 #define MIIM_INDICATOR_ADDR             0x30
0051 #define MIIMRD_FIELD_ADDR               0x34
0052
0053 #define MDIO_CSR_OFFSET         0x5000
0054
0055 #define REG_ADDR_POS            0
0056 #define REG_ADDR_LEN            5
0057 #define PHY_ADDR_POS            8
0058 #define PHY_ADDR_LEN            5
0059
0060 #define HSTMIIMWRDAT_POS        0
0061 #define HSTMIIMWRDAT_LEN        16
0062 #define HSTPHYADX_POS           23
0063 #define HSTPHYADX_LEN           5
0064 #define HSTREGADX_POS           18
0065 #define HSTREGADX_LEN           5
0066 #define HSTLDCMD            BIT(3)
0067 #define HSTMIIMCMD_POS          0
0068 #define HSTMIIMCMD_LEN          3
0069
0070 #define BUSY_MASK           BIT(0)
0071 #define READ_CYCLE_MASK         BIT(0)
0072
0073 enum xgene_enet_cmd {
0074     XGENE_ENET_WR_CMD = BIT(31),
0075     XGENE_ENET_RD_CMD = BIT(30)
0076 };
0077
0078 enum {
0079     MIIM_CMD_IDLE,
0080     MIIM_CMD_LEGACY_WRITE,
0081     MIIM_CMD_LEGACY_READ,
0082 };
0083
0084 enum xgene_mdio_id {
0085     XGENE_MDIO_RGMII = 1,
0086     XGENE_MDIO_XFI
0087 };
0088
0089 struct xgene_mdio_pdata {
0090     struct clk *clk;
0091     struct device *dev;
0092     void __iomem *mac_csr_addr;
0093     void __iomem *diag_csr_addr;
0094     void __iomem *mdio_csr_addr;
0095     struct mii_bus *mdio_bus;
0096     int mdio_id;
0097     spinlock_t mac_lock; /* mac lock */
0098 };
0099
0100 /* Set the specified value into a bit-field defined by its starting position
0101  * and length within a single u64.
0102  */
0103 static inline u64 xgene_enet_set_field_value(int pos, int len, u64 val)
0104 {
0105     return (val & ((1ULL << len) - 1)) << pos;
0106 }
0107
0108 #define SET_VAL(field, val) \
0109         xgene_enet_set_field_value(field ## _POS, field ## _LEN, val)
0110
0111 #define SET_BIT(field) \
0112         xgene_enet_set_field_value(field ## _POS, 1, 1)
0113
0114 /* Get the value from a bit-field defined by its starting position
0115  * and length within the specified u64.
0116  */
0117 static inline u64 xgene_enet_get_field_value(int pos, int len, u64 src)
0118 {
0119     return (src >> pos) & ((1ULL << len) - 1);
0120 }
0121
0122 #define GET_VAL(field, src) \
0123         xgene_enet_get_field_value(field ## _POS, field ## _LEN, src)
0124
0125 #define GET_BIT(field, src) \
0126         xgene_enet_get_field_value(field ## _POS, 1, src)
0127
0128 u32 xgene_mdio_rd_mac(struct xgene_mdio_pdata *pdata, u32 rd_addr);
0129 void xgene_mdio_wr_mac(struct xgene_mdio_pdata *pdata, u32 wr_addr, u32 data);
0130 int xgene_mdio_rgmii_read(struct mii_bus *bus, int phy_id, int reg);
0131 int xgene_mdio_rgmii_write(struct mii_bus *bus, int phy_id, int reg, u16 data);
0132 struct phy_device *xgene_enet_phy_register(struct mii_bus *bus, int phy_addr);
0133
0134 #endif  /* __MDIO_XGENE_H__ */