include/linux/mc146818rtc.h

0001 /* mc146818rtc.h - register definitions for the Real-Time-Clock / CMOS RAM
0002  * Copyright Torsten Duwe <duwe@informatik.uni-erlangen.de> 1993
0003  * derived from Data Sheet, Copyright Motorola 1984 (!).
0004  * It was written to be part of the Linux operating system.
0005  */
0006 /* permission is hereby granted to copy, modify and redistribute this code
0007  * in terms of the GNU Library General Public License, Version 2 or later,
0008  * at your option.
0009  */
0010
0011 #ifndef _MC146818RTC_H
0012 #define _MC146818RTC_H
0013
0014 #include <asm/io.h>
0015 #include <linux/rtc.h>          /* get the user-level API */
0016 #include <asm/mc146818rtc.h>        /* register access macros */
0017 #include <linux/bcd.h>
0018 #include <linux/delay.h>
0019 #include <linux/pm-trace.h>
0020
0021 #ifdef __KERNEL__
0022 #include <linux/spinlock.h>     /* spinlock_t */
0023 extern spinlock_t rtc_lock;     /* serialize CMOS RAM access */
0024
0025 /* Some RTCs extend the mc146818 register set to support alarms of more
0026  * than 24 hours in the future; or dates that include a century code.
0027  * This platform_data structure can pass this information to the driver.
0028  *
0029  * Also, some platforms need suspend()/resume() hooks to kick in special
0030  * handling of wake alarms, e.g. activating ACPI BIOS hooks or setting up
0031  * a separate wakeup alarm used by some almost-clone chips.
0032  */
0033 struct cmos_rtc_board_info {
0034     void    (*wake_on)(struct device *dev);
0035     void    (*wake_off)(struct device *dev);
0036
0037     u32 flags;
0038 #define CMOS_RTC_FLAGS_NOFREQ   (1 << 0)
0039     int address_space;
0040
0041     u8  rtc_day_alarm;      /* zero, or register index */
0042     u8  rtc_mon_alarm;      /* zero, or register index */
0043     u8  rtc_century;        /* zero, or register index */
0044 };
0045 #endif
0046
0047 /**********************************************************************
0048  * register summary
0049  **********************************************************************/
0050 #define RTC_SECONDS     0
0051 #define RTC_SECONDS_ALARM   1
0052 #define RTC_MINUTES     2
0053 #define RTC_MINUTES_ALARM   3
0054 #define RTC_HOURS       4
0055 #define RTC_HOURS_ALARM     5
0056 /* RTC_*_alarm is always true if 2 MSBs are set */
0057 # define RTC_ALARM_DONT_CARE    0xC0
0058
0059 #define RTC_DAY_OF_WEEK     6
0060 #define RTC_DAY_OF_MONTH    7
0061 #define RTC_MONTH       8
0062 #define RTC_YEAR        9
0063
0064 /* control registers - Moto names
0065  */
0066 #define RTC_REG_A       10
0067 #define RTC_REG_B       11
0068 #define RTC_REG_C       12
0069 #define RTC_REG_D       13
0070
0071 /**********************************************************************
0072  * register details
0073  **********************************************************************/
0074 #define RTC_FREQ_SELECT RTC_REG_A
0075
0076 /* update-in-progress  - set to "1" 244 microsecs before RTC goes off the bus,
0077  * reset after update (may take 1.984ms @ 32768Hz RefClock) is complete,
0078  * totalling to a max high interval of 2.228 ms.
0079  */
0080 # define RTC_UIP        0x80
0081 # define RTC_DIV_CTL        0x70
0082    /* divider control: refclock values 4.194 / 1.049 MHz / 32.768 kHz */
0083 #  define RTC_REF_CLCK_4MHZ 0x00
0084 #  define RTC_REF_CLCK_1MHZ 0x10
0085 #  define RTC_REF_CLCK_32KHZ    0x20
0086    /* 2 values for divider stage reset, others for "testing purposes only" */
0087 #  define RTC_DIV_RESET1    0x60
0088 #  define RTC_DIV_RESET2    0x70
0089    /* In AMD BKDG bit 5 and 6 are reserved, bit 4 is for select dv0 bank */
0090 #  define RTC_AMD_BANK_SELECT   0x10
0091   /* Periodic intr. / Square wave rate select. 0=none, 1=32.8kHz,... 15=2Hz */
0092 # define RTC_RATE_SELECT    0x0F
0093
0094 /**********************************************************************/
0095 #define RTC_CONTROL RTC_REG_B
0096 # define RTC_SET 0x80       /* disable updates for clock setting */
0097 # define RTC_PIE 0x40       /* periodic interrupt enable */
0098 # define RTC_AIE 0x20       /* alarm interrupt enable */
0099 # define RTC_UIE 0x10       /* update-finished interrupt enable */
0100 # define RTC_SQWE 0x08      /* enable square-wave output */
0101 # define RTC_DM_BINARY 0x04 /* all time/date values are BCD if clear */
0102 # define RTC_24H 0x02       /* 24 hour mode - else hours bit 7 means pm */
0103 # define RTC_DST_EN 0x01    /* auto switch DST - works f. USA only */
0104
0105 /**********************************************************************/
0106 #define RTC_INTR_FLAGS  RTC_REG_C
0107 /* caution - cleared by read */
0108 # define RTC_IRQF 0x80      /* any of the following 3 is active */
0109 # define RTC_PF 0x40
0110 # define RTC_AF 0x20
0111 # define RTC_UF 0x10
0112
0113 /**********************************************************************/
0114 #define RTC_VALID   RTC_REG_D
0115 # define RTC_VRT 0x80       /* valid RAM and time */
0116 /**********************************************************************/
0117
0118 #ifndef ARCH_RTC_LOCATION   /* Override by <asm/mc146818rtc.h>? */
0119
0120 #define RTC_IO_EXTENT   0x8
0121 #define RTC_IO_EXTENT_USED  0x2
0122 #define RTC_IOMAPPED    1   /* Default to I/O mapping. */
0123
0124 #else
0125 #define RTC_IO_EXTENT_USED      RTC_IO_EXTENT
0126 #endif /* ARCH_RTC_LOCATION */
0127
0128 bool mc146818_does_rtc_work(void);
0129 int mc146818_get_time(struct rtc_time *time);
0130 int mc146818_set_time(struct rtc_time *time);
0131
0132 bool mc146818_avoid_UIP(void (*callback)(unsigned char seconds, void *param),
0133             void *param);
0134
0135 #endif /* _MC146818RTC_H */