linux/irqchip/irq-bcm2836.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Root interrupt controller for the BCM2836 (Raspberry Pi 2).
0004  *
0005  * Copyright 2015 Broadcom
0006  */
0007
0008 #define LOCAL_CONTROL           0x000
0009 #define LOCAL_PRESCALER         0x008
0010
0011 /*
0012  * The low 2 bits identify the CPU that the GPU IRQ goes to, and the
0013  * next 2 bits identify the CPU that the GPU FIQ goes to.
0014  */
0015 #define LOCAL_GPU_ROUTING       0x00c
0016 /* When setting bits 0-3, enables PMU interrupts on that CPU. */
0017 #define LOCAL_PM_ROUTING_SET        0x010
0018 /* When setting bits 0-3, disables PMU interrupts on that CPU. */
0019 #define LOCAL_PM_ROUTING_CLR        0x014
0020 /*
0021  * The low 4 bits of this are the CPU's timer IRQ enables, and the
0022  * next 4 bits are the CPU's timer FIQ enables (which override the IRQ
0023  * bits).
0024  */
0025 #define LOCAL_TIMER_INT_CONTROL0    0x040
0026 /*
0027  * The low 4 bits of this are the CPU's per-mailbox IRQ enables, and
0028  * the next 4 bits are the CPU's per-mailbox FIQ enables (which
0029  * override the IRQ bits).
0030  */
0031 #define LOCAL_MAILBOX_INT_CONTROL0  0x050
0032 /*
0033  * The CPU's interrupt status register.  Bits are defined by the
0034  * LOCAL_IRQ_* bits below.
0035  */
0036 #define LOCAL_IRQ_PENDING0      0x060
0037 /* Same status bits as above, but for FIQ. */
0038 #define LOCAL_FIQ_PENDING0      0x070
0039 /*
0040  * Mailbox write-to-set bits.  There are 16 mailboxes, 4 per CPU, and
0041  * these bits are organized by mailbox number and then CPU number.  We
0042  * use mailbox 0 for IPIs.  The mailbox's interrupt is raised while
0043  * any bit is set.
0044  */
0045 #define LOCAL_MAILBOX0_SET0     0x080
0046 #define LOCAL_MAILBOX3_SET0     0x08c
0047 /* Mailbox write-to-clear bits. */
0048 #define LOCAL_MAILBOX0_CLR0     0x0c0
0049 #define LOCAL_MAILBOX3_CLR0     0x0cc
0050
0051 #define LOCAL_IRQ_CNTPSIRQ  0
0052 #define LOCAL_IRQ_CNTPNSIRQ 1
0053 #define LOCAL_IRQ_CNTHPIRQ  2
0054 #define LOCAL_IRQ_CNTVIRQ   3
0055 #define LOCAL_IRQ_MAILBOX0  4
0056 #define LOCAL_IRQ_MAILBOX1  5
0057 #define LOCAL_IRQ_MAILBOX2  6
0058 #define LOCAL_IRQ_MAILBOX3  7
0059 #define LOCAL_IRQ_GPU_FAST  8
0060 #define LOCAL_IRQ_PMU_FAST  9
0061 #define LAST_IRQ        LOCAL_IRQ_PMU_FAST