linux/irqchip/arm-gic.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  *  include/linux/irqchip/arm-gic.h
0004  *
0005  *  Copyright (C) 2002 ARM Limited, All Rights Reserved.
0006  */
0007 #ifndef __LINUX_IRQCHIP_ARM_GIC_H
0008 #define __LINUX_IRQCHIP_ARM_GIC_H
0009
0010 #define GIC_CPU_CTRL            0x00
0011 #define GIC_CPU_PRIMASK         0x04
0012 #define GIC_CPU_BINPOINT        0x08
0013 #define GIC_CPU_INTACK          0x0c
0014 #define GIC_CPU_EOI         0x10
0015 #define GIC_CPU_RUNNINGPRI      0x14
0016 #define GIC_CPU_HIGHPRI         0x18
0017 #define GIC_CPU_ALIAS_BINPOINT      0x1c
0018 #define GIC_CPU_ACTIVEPRIO      0xd0
0019 #define GIC_CPU_IDENT           0xfc
0020 #define GIC_CPU_DEACTIVATE      0x1000
0021
0022 #define GICC_ENABLE         0x1
0023 #define GICC_INT_PRI_THRESHOLD      0xf0
0024
0025 #define GIC_CPU_CTRL_EnableGrp0_SHIFT   0
0026 #define GIC_CPU_CTRL_EnableGrp0     (1 << GIC_CPU_CTRL_EnableGrp0_SHIFT)
0027 #define GIC_CPU_CTRL_EnableGrp1_SHIFT   1
0028 #define GIC_CPU_CTRL_EnableGrp1     (1 << GIC_CPU_CTRL_EnableGrp1_SHIFT)
0029 #define GIC_CPU_CTRL_AckCtl_SHIFT   2
0030 #define GIC_CPU_CTRL_AckCtl     (1 << GIC_CPU_CTRL_AckCtl_SHIFT)
0031 #define GIC_CPU_CTRL_FIQEn_SHIFT    3
0032 #define GIC_CPU_CTRL_FIQEn      (1 << GIC_CPU_CTRL_FIQEn_SHIFT)
0033 #define GIC_CPU_CTRL_CBPR_SHIFT     4
0034 #define GIC_CPU_CTRL_CBPR       (1 << GIC_CPU_CTRL_CBPR_SHIFT)
0035 #define GIC_CPU_CTRL_EOImodeNS_SHIFT    9
0036 #define GIC_CPU_CTRL_EOImodeNS      (1 << GIC_CPU_CTRL_EOImodeNS_SHIFT)
0037
0038 #define GICC_IAR_INT_ID_MASK        0x3ff
0039 #define GICC_INT_SPURIOUS       1023
0040 #define GICC_DIS_BYPASS_MASK        0x1e0
0041
0042 #define GIC_DIST_CTRL           0x000
0043 #define GIC_DIST_CTR            0x004
0044 #define GIC_DIST_IIDR           0x008
0045 #define GIC_DIST_IGROUP         0x080
0046 #define GIC_DIST_ENABLE_SET     0x100
0047 #define GIC_DIST_ENABLE_CLEAR       0x180
0048 #define GIC_DIST_PENDING_SET        0x200
0049 #define GIC_DIST_PENDING_CLEAR      0x280
0050 #define GIC_DIST_ACTIVE_SET     0x300
0051 #define GIC_DIST_ACTIVE_CLEAR       0x380
0052 #define GIC_DIST_PRI            0x400
0053 #define GIC_DIST_TARGET         0x800
0054 #define GIC_DIST_CONFIG         0xc00
0055 #define GIC_DIST_SOFTINT        0xf00
0056 #define GIC_DIST_SGI_PENDING_CLEAR  0xf10
0057 #define GIC_DIST_SGI_PENDING_SET    0xf20
0058
0059 #define GICD_ENABLE         0x1
0060 #define GICD_DISABLE            0x0
0061 #define GICD_INT_ACTLOW_LVLTRIG     0x0
0062 #define GICD_INT_EN_CLR_X32     0xffffffff
0063 #define GICD_INT_EN_SET_SGI     0x0000ffff
0064 #define GICD_INT_EN_CLR_PPI     0xffff0000
0065
0066 #define GICD_IIDR_IMPLEMENTER_SHIFT 0
0067 #define GICD_IIDR_IMPLEMENTER_MASK  (0xfff << GICD_IIDR_IMPLEMENTER_SHIFT)
0068 #define GICD_IIDR_REVISION_SHIFT    12
0069 #define GICD_IIDR_REVISION_MASK     (0xf << GICD_IIDR_REVISION_SHIFT)
0070 #define GICD_IIDR_VARIANT_SHIFT     16
0071 #define GICD_IIDR_VARIANT_MASK      (0xf << GICD_IIDR_VARIANT_SHIFT)
0072 #define GICD_IIDR_PRODUCT_ID_SHIFT  24
0073 #define GICD_IIDR_PRODUCT_ID_MASK   (0xff << GICD_IIDR_PRODUCT_ID_SHIFT)
0074
0075
0076 #define GICH_HCR            0x0
0077 #define GICH_VTR            0x4
0078 #define GICH_VMCR           0x8
0079 #define GICH_MISR           0x10
0080 #define GICH_EISR0          0x20
0081 #define GICH_EISR1          0x24
0082 #define GICH_ELRSR0             0x30
0083 #define GICH_ELRSR1             0x34
0084 #define GICH_APR            0xf0
0085 #define GICH_LR0            0x100
0086
0087 #define GICH_HCR_EN         (1 << 0)
0088 #define GICH_HCR_UIE            (1 << 1)
0089 #define GICH_HCR_NPIE           (1 << 3)
0090
0091 #define GICH_LR_VIRTUALID       (0x3ff << 0)
0092 #define GICH_LR_PHYSID_CPUID_SHIFT  (10)
0093 #define GICH_LR_PHYSID_CPUID        (0x3ff << GICH_LR_PHYSID_CPUID_SHIFT)
0094 #define GICH_LR_PRIORITY_SHIFT      23
0095 #define GICH_LR_STATE           (3 << 28)
0096 #define GICH_LR_PENDING_BIT     (1 << 28)
0097 #define GICH_LR_ACTIVE_BIT      (1 << 29)
0098 #define GICH_LR_EOI         (1 << 19)
0099 #define GICH_LR_GROUP1          (1 << 30)
0100 #define GICH_LR_HW          (1 << 31)
0101
0102 #define GICH_VMCR_ENABLE_GRP0_SHIFT 0
0103 #define GICH_VMCR_ENABLE_GRP0_MASK  (1 << GICH_VMCR_ENABLE_GRP0_SHIFT)
0104 #define GICH_VMCR_ENABLE_GRP1_SHIFT 1
0105 #define GICH_VMCR_ENABLE_GRP1_MASK  (1 << GICH_VMCR_ENABLE_GRP1_SHIFT)
0106 #define GICH_VMCR_ACK_CTL_SHIFT     2
0107 #define GICH_VMCR_ACK_CTL_MASK      (1 << GICH_VMCR_ACK_CTL_SHIFT)
0108 #define GICH_VMCR_FIQ_EN_SHIFT      3
0109 #define GICH_VMCR_FIQ_EN_MASK       (1 << GICH_VMCR_FIQ_EN_SHIFT)
0110 #define GICH_VMCR_CBPR_SHIFT        4
0111 #define GICH_VMCR_CBPR_MASK     (1 << GICH_VMCR_CBPR_SHIFT)
0112 #define GICH_VMCR_EOI_MODE_SHIFT    9
0113 #define GICH_VMCR_EOI_MODE_MASK     (1 << GICH_VMCR_EOI_MODE_SHIFT)
0114
0115 #define GICH_VMCR_PRIMASK_SHIFT     27
0116 #define GICH_VMCR_PRIMASK_MASK      (0x1f << GICH_VMCR_PRIMASK_SHIFT)
0117 #define GICH_VMCR_BINPOINT_SHIFT    21
0118 #define GICH_VMCR_BINPOINT_MASK     (0x7 << GICH_VMCR_BINPOINT_SHIFT)
0119 #define GICH_VMCR_ALIAS_BINPOINT_SHIFT  18
0120 #define GICH_VMCR_ALIAS_BINPOINT_MASK   (0x7 << GICH_VMCR_ALIAS_BINPOINT_SHIFT)
0121
0122 #define GICH_MISR_EOI           (1 << 0)
0123 #define GICH_MISR_U         (1 << 1)
0124
0125 #define GICV_PMR_PRIORITY_SHIFT     3
0126 #define GICV_PMR_PRIORITY_MASK      (0x1f << GICV_PMR_PRIORITY_SHIFT)
0127
0128 #ifndef __ASSEMBLY__
0129
0130 #include <linux/irqdomain.h>
0131
0132 struct device_node;
0133 struct gic_chip_data;
0134
0135 void gic_cascade_irq(unsigned int gic_nr, unsigned int irq);
0136 int gic_cpu_if_down(unsigned int gic_nr);
0137 void gic_cpu_save(struct gic_chip_data *gic);
0138 void gic_cpu_restore(struct gic_chip_data *gic);
0139 void gic_dist_save(struct gic_chip_data *gic);
0140 void gic_dist_restore(struct gic_chip_data *gic);
0141
0142 /*
0143  * Subdrivers that need some preparatory work can initialize their
0144  * chips and call this to register their GICs.
0145  */
0146 int gic_of_init(struct device_node *node, struct device_node *parent);
0147
0148 /*
0149  * Initialises and registers a non-root or child GIC chip. Memory for
0150  * the gic_chip_data structure is dynamically allocated.
0151  */
0152 int gic_of_init_child(struct device *dev, struct gic_chip_data **gic, int irq);
0153
0154 /*
0155  * Legacy platforms not converted to DT yet must use this to init
0156  * their GIC
0157  */
0158 void gic_init(void __iomem *dist , void __iomem *cpu);
0159
0160 void gic_send_sgi(unsigned int cpu_id, unsigned int irq);
0161 int gic_get_cpu_id(unsigned int cpu);
0162 void gic_migrate_target(unsigned int new_cpu_id);
0163 unsigned long gic_get_sgir_physaddr(void);
0164
0165 #endif /* __ASSEMBLY */
0166 #endif