iio/frequency/adf4350.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * ADF4350/ADF4351 SPI PLL driver
0004  *
0005  * Copyright 2012-2013 Analog Devices Inc.
0006  */
0007
0008 #ifndef IIO_PLL_ADF4350_H_
0009 #define IIO_PLL_ADF4350_H_
0010
0011 /* Registers */
0012 #define ADF4350_REG0    0
0013 #define ADF4350_REG1    1
0014 #define ADF4350_REG2    2
0015 #define ADF4350_REG3    3
0016 #define ADF4350_REG4    4
0017 #define ADF4350_REG5    5
0018
0019 /* REG0 Bit Definitions */
0020 #define ADF4350_REG0_FRACT(x)           (((x) & 0xFFF) << 3)
0021 #define ADF4350_REG0_INT(x)         (((x) & 0xFFFF) << 15)
0022
0023 /* REG1 Bit Definitions */
0024 #define ADF4350_REG1_MOD(x)         (((x) & 0xFFF) << 3)
0025 #define ADF4350_REG1_PHASE(x)           (((x) & 0xFFF) << 15)
0026 #define ADF4350_REG1_PRESCALER          (1 << 27)
0027
0028 /* REG2 Bit Definitions */
0029 #define ADF4350_REG2_COUNTER_RESET_EN       (1 << 3)
0030 #define ADF4350_REG2_CP_THREESTATE_EN       (1 << 4)
0031 #define ADF4350_REG2_POWER_DOWN_EN      (1 << 5)
0032 #define ADF4350_REG2_PD_POLARITY_POS        (1 << 6)
0033 #define ADF4350_REG2_LDP_6ns            (1 << 7)
0034 #define ADF4350_REG2_LDP_10ns           (0 << 7)
0035 #define ADF4350_REG2_LDF_FRACT_N        (0 << 8)
0036 #define ADF4350_REG2_LDF_INT_N          (1 << 8)
0037 #define ADF4350_REG2_CHARGE_PUMP_CURR_uA(x) (((((x)-312) / 312) & 0xF) << 9)
0038 #define ADF4350_REG2_DOUBLE_BUFF_EN     (1 << 13)
0039 #define ADF4350_REG2_10BIT_R_CNT(x)     ((x) << 14)
0040 #define ADF4350_REG2_RDIV2_EN           (1 << 24)
0041 #define ADF4350_REG2_RMULT2_EN          (1 << 25)
0042 #define ADF4350_REG2_MUXOUT(x)          ((x) << 26)
0043 #define ADF4350_REG2_NOISE_MODE(x)      (((unsigned)(x)) << 29)
0044 #define ADF4350_MUXOUT_THREESTATE       0
0045 #define ADF4350_MUXOUT_DVDD         1
0046 #define ADF4350_MUXOUT_GND          2
0047 #define ADF4350_MUXOUT_R_DIV_OUT        3
0048 #define ADF4350_MUXOUT_N_DIV_OUT        4
0049 #define ADF4350_MUXOUT_ANALOG_LOCK_DETECT   5
0050 #define ADF4350_MUXOUT_DIGITAL_LOCK_DETECT  6
0051
0052 /* REG3 Bit Definitions */
0053 #define ADF4350_REG3_12BIT_CLKDIV(x)        ((x) << 3)
0054 #define ADF4350_REG3_12BIT_CLKDIV_MODE(x)   ((x) << 16)
0055 #define ADF4350_REG3_12BIT_CSR_EN       (1 << 18)
0056 #define ADF4351_REG3_CHARGE_CANCELLATION_EN (1 << 21)
0057 #define ADF4351_REG3_ANTI_BACKLASH_3ns_EN   (1 << 22)
0058 #define ADF4351_REG3_BAND_SEL_CLOCK_MODE_HIGH   (1 << 23)
0059
0060 /* REG4 Bit Definitions */
0061 #define ADF4350_REG4_OUTPUT_PWR(x)      ((x) << 3)
0062 #define ADF4350_REG4_RF_OUT_EN          (1 << 5)
0063 #define ADF4350_REG4_AUX_OUTPUT_PWR(x)      ((x) << 6)
0064 #define ADF4350_REG4_AUX_OUTPUT_EN      (1 << 8)
0065 #define ADF4350_REG4_AUX_OUTPUT_FUND        (1 << 9)
0066 #define ADF4350_REG4_AUX_OUTPUT_DIV     (0 << 9)
0067 #define ADF4350_REG4_MUTE_TILL_LOCK_EN      (1 << 10)
0068 #define ADF4350_REG4_VCO_PWRDOWN_EN     (1 << 11)
0069 #define ADF4350_REG4_8BIT_BAND_SEL_CLKDIV(x)    ((x) << 12)
0070 #define ADF4350_REG4_RF_DIV_SEL(x)      ((x) << 20)
0071 #define ADF4350_REG4_FEEDBACK_DIVIDED       (0 << 23)
0072 #define ADF4350_REG4_FEEDBACK_FUND      (1 << 23)
0073
0074 /* REG5 Bit Definitions */
0075 #define ADF4350_REG5_LD_PIN_MODE_LOW        (0 << 22)
0076 #define ADF4350_REG5_LD_PIN_MODE_DIGITAL    (1 << 22)
0077 #define ADF4350_REG5_LD_PIN_MODE_HIGH       (3 << 22)
0078
0079 /* Specifications */
0080 #define ADF4350_MAX_OUT_FREQ        4400000000ULL /* Hz */
0081 #define ADF4350_MIN_OUT_FREQ        137500000 /* Hz */
0082 #define ADF4351_MIN_OUT_FREQ        34375000 /* Hz */
0083 #define ADF4350_MIN_VCO_FREQ        2200000000ULL /* Hz */
0084 #define ADF4350_MAX_FREQ_45_PRESC   3000000000ULL /* Hz */
0085 #define ADF4350_MAX_FREQ_PFD        32000000 /* Hz */
0086 #define ADF4350_MAX_BANDSEL_CLK     125000 /* Hz */
0087 #define ADF4350_MAX_FREQ_REFIN      250000000 /* Hz */
0088 #define ADF4350_MAX_MODULUS     4095
0089 #define ADF4350_MAX_R_CNT       1023
0090
0091
0092 /**
0093  * struct adf4350_platform_data - platform specific information
0094  * @name:       Optional device name.
0095  * @clkin:      REFin frequency in Hz.
0096  * @channel_spacing:    Channel spacing in Hz (influences MODULUS).
0097  * @power_up_frequency: Optional, If set in Hz the PLL tunes to the desired
0098  *          frequency on probe.
0099  * @ref_div_factor: Optional, if set the driver skips dynamic calculation
0100  *          and uses this default value instead.
0101  * @ref_doubler_en: Enables reference doubler.
0102  * @ref_div2_en:    Enables reference divider.
0103  * @r2_user_settings:   User defined settings for ADF4350/1 REGISTER_2.
0104  * @r3_user_settings:   User defined settings for ADF4350/1 REGISTER_3.
0105  * @r4_user_settings:   User defined settings for ADF4350/1 REGISTER_4.
0106  */
0107
0108 struct adf4350_platform_data {
0109     char            name[32];
0110     unsigned long       clkin;
0111     unsigned long       channel_spacing;
0112     unsigned long long  power_up_frequency;
0113
0114     unsigned short      ref_div_factor; /* 10-bit R counter */
0115     bool            ref_doubler_en;
0116     bool            ref_div2_en;
0117
0118     unsigned        r2_user_settings;
0119     unsigned        r3_user_settings;
0120     unsigned        r4_user_settings;
0121 };
0122
0123 #endif /* IIO_PLL_ADF4350_H_ */