iio/frequency/ad9523.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * AD9523 SPI Low Jitter Clock Generator
0004  *
0005  * Copyright 2012 Analog Devices Inc.
0006  */
0007
0008 #ifndef IIO_FREQUENCY_AD9523_H_
0009 #define IIO_FREQUENCY_AD9523_H_
0010
0011 enum outp_drv_mode {
0012     TRISTATE,
0013     LVPECL_8mA,
0014     LVDS_4mA,
0015     LVDS_7mA,
0016     HSTL0_16mA,
0017     HSTL1_8mA,
0018     CMOS_CONF1,
0019     CMOS_CONF2,
0020     CMOS_CONF3,
0021     CMOS_CONF4,
0022     CMOS_CONF5,
0023     CMOS_CONF6,
0024     CMOS_CONF7,
0025     CMOS_CONF8,
0026     CMOS_CONF9
0027 };
0028
0029 enum ref_sel_mode {
0030     NONEREVERTIVE_STAY_ON_REFB,
0031     REVERT_TO_REFA,
0032     SELECT_REFA,
0033     SELECT_REFB,
0034     EXT_REF_SEL
0035 };
0036
0037 /**
0038  * struct ad9523_channel_spec - Output channel configuration
0039  *
0040  * @channel_num: Output channel number.
0041  * @divider_output_invert_en: Invert the polarity of the output clock.
0042  * @sync_ignore_en: Ignore chip-level SYNC signal.
0043  * @low_power_mode_en: Reduce power used in the differential output modes.
0044  * @use_alt_clock_src: Channel divider uses alternative clk source.
0045  * @output_dis: Disables, powers down the entire channel.
0046  * @driver_mode: Output driver mode (logic level family).
0047  * @divider_phase: Divider initial phase after a SYNC. Range 0..63
0048            LSB = 1/2 of a period of the divider input clock.
0049  * @channel_divider: 10-bit channel divider.
0050  * @extended_name: Optional descriptive channel name.
0051  */
0052
0053 struct ad9523_channel_spec {
0054     unsigned        channel_num;
0055     bool            divider_output_invert_en;
0056     bool            sync_ignore_en;
0057     bool            low_power_mode_en;
0058                  /* CH0..CH3 VCXO, CH4..CH9 VCO2 */
0059     bool            use_alt_clock_src;
0060     bool            output_dis;
0061     enum outp_drv_mode  driver_mode;
0062     unsigned char       divider_phase;
0063     unsigned short      channel_divider;
0064     char            extended_name[16];
0065 };
0066
0067 enum pll1_rzero_resistor {
0068     RZERO_883_OHM,
0069     RZERO_677_OHM,
0070     RZERO_341_OHM,
0071     RZERO_135_OHM,
0072     RZERO_10_OHM,
0073     RZERO_USE_EXT_RES = 8,
0074 };
0075
0076 enum rpole2_resistor {
0077     RPOLE2_900_OHM,
0078     RPOLE2_450_OHM,
0079     RPOLE2_300_OHM,
0080     RPOLE2_225_OHM,
0081 };
0082
0083 enum rzero_resistor {
0084     RZERO_3250_OHM,
0085     RZERO_2750_OHM,
0086     RZERO_2250_OHM,
0087     RZERO_2100_OHM,
0088     RZERO_3000_OHM,
0089     RZERO_2500_OHM,
0090     RZERO_2000_OHM,
0091     RZERO_1850_OHM,
0092 };
0093
0094 enum cpole1_capacitor {
0095     CPOLE1_0_PF,
0096     CPOLE1_8_PF,
0097     CPOLE1_16_PF,
0098     CPOLE1_24_PF,
0099     _CPOLE1_24_PF, /* place holder */
0100     CPOLE1_32_PF,
0101     CPOLE1_40_PF,
0102     CPOLE1_48_PF,
0103 };
0104
0105 /**
0106  * struct ad9523_platform_data - platform specific information
0107  *
0108  * @vcxo_freq: External VCXO frequency in Hz
0109  * @refa_diff_rcv_en: REFA differential/single-ended input selection.
0110  * @refb_diff_rcv_en: REFB differential/single-ended input selection.
0111  * @zd_in_diff_en: Zero Delay differential/single-ended input selection.
0112  * @osc_in_diff_en: OSC differential/ single-ended input selection.
0113  * @refa_cmos_neg_inp_en: REFA single-ended neg./pos. input enable.
0114  * @refb_cmos_neg_inp_en: REFB single-ended neg./pos. input enable.
0115  * @zd_in_cmos_neg_inp_en: Zero Delay single-ended neg./pos. input enable.
0116  * @osc_in_cmos_neg_inp_en: OSC single-ended neg./pos. input enable.
0117  * @refa_r_div: PLL1 10-bit REFA R divider.
0118  * @refb_r_div: PLL1 10-bit REFB R divider.
0119  * @pll1_feedback_div: PLL1 10-bit Feedback N divider.
0120  * @pll1_charge_pump_current_nA: Magnitude of PLL1 charge pump current (nA).
0121  * @zero_delay_mode_internal_en: Internal, external Zero Delay mode selection.
0122  * @osc_in_feedback_en: PLL1 feedback path, local feedback from
0123  *          the OSC_IN receiver or zero delay mode
0124  * @pll1_loop_filter_rzero: PLL1 Loop Filter Zero Resistor selection.
0125  * @ref_mode: Reference selection mode.
0126  * @pll2_charge_pump_current_nA: Magnitude of PLL2 charge pump current (nA).
0127  * @pll2_ndiv_a_cnt: PLL2 Feedback N-divider, A Counter, range 0..4.
0128  * @pll2_ndiv_b_cnt: PLL2 Feedback N-divider, B Counter, range 0..63.
0129  * @pll2_freq_doubler_en: PLL2 frequency doubler enable.
0130  * @pll2_r2_div: PLL2 R2 divider, range 0..31.
0131  * @pll2_vco_div_m1: VCO1 divider, range 3..5.
0132  * @pll2_vco_div_m2: VCO2 divider, range 3..5.
0133  * @rpole2: PLL2 loop filter Rpole resistor value.
0134  * @rzero: PLL2 loop filter Rzero resistor value.
0135  * @cpole1: PLL2 loop filter Cpole capacitor value.
0136  * @rzero_bypass_en: PLL2 loop filter Rzero bypass enable.
0137  * @num_channels: Array size of struct ad9523_channel_spec.
0138  * @channels: Pointer to channel array.
0139  * @name: Optional alternative iio device name.
0140  */
0141
0142 struct ad9523_platform_data {
0143     unsigned long vcxo_freq;
0144
0145     /* Differential/ Single-Ended Input Configuration */
0146     bool                refa_diff_rcv_en;
0147     bool                refb_diff_rcv_en;
0148     bool                zd_in_diff_en;
0149     bool                osc_in_diff_en;
0150
0151     /*
0152      * Valid if differential input disabled
0153      * if false defaults to pos input
0154      */
0155     bool                refa_cmos_neg_inp_en;
0156     bool                refb_cmos_neg_inp_en;
0157     bool                zd_in_cmos_neg_inp_en;
0158     bool                osc_in_cmos_neg_inp_en;
0159
0160     /* PLL1 Setting */
0161     unsigned short          refa_r_div;
0162     unsigned short          refb_r_div;
0163     unsigned short          pll1_feedback_div;
0164     unsigned short          pll1_charge_pump_current_nA;
0165     bool                zero_delay_mode_internal_en;
0166     bool                osc_in_feedback_en;
0167     enum pll1_rzero_resistor    pll1_loop_filter_rzero;
0168
0169     /* Reference */
0170     enum ref_sel_mode       ref_mode;
0171
0172     /* PLL2 Setting */
0173     unsigned int            pll2_charge_pump_current_nA;
0174     unsigned char           pll2_ndiv_a_cnt;
0175     unsigned char           pll2_ndiv_b_cnt;
0176     bool                pll2_freq_doubler_en;
0177     unsigned char           pll2_r2_div;
0178     unsigned char           pll2_vco_div_m1; /* 3..5 */
0179     unsigned char           pll2_vco_div_m2; /* 3..5 */
0180
0181     /* Loop Filter PLL2 */
0182     enum rpole2_resistor        rpole2;
0183     enum rzero_resistor     rzero;
0184     enum cpole1_capacitor       cpole1;
0185     bool                rzero_bypass_en;
0186
0187     /* Output Channel Configuration */
0188     int             num_channels;
0189     struct ad9523_channel_spec  *channels;
0190
0191     char                name[SPI_NAME_SIZE];
0192 };
0193
0194 #endif /* IIO_FREQUENCY_AD9523_H_ */