include/linux/hpet.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef __HPET__
0003 #define __HPET__ 1
0004
0005 #include <uapi/linux/hpet.h>
0006
0007
0008 /*
0009  * Offsets into HPET Registers
0010  */
0011
0012 struct hpet {
0013     u64 hpet_cap;       /* capabilities */
0014     u64 res0;       /* reserved */
0015     u64 hpet_config;    /* configuration */
0016     u64 res1;       /* reserved */
0017     u64 hpet_isr;       /* interrupt status reg */
0018     u64 res2[25];       /* reserved */
0019     union {         /* main counter */
0020         u64 _hpet_mc64;
0021         u32 _hpet_mc32;
0022         unsigned long _hpet_mc;
0023     } _u0;
0024     u64 res3;       /* reserved */
0025     struct hpet_timer {
0026         u64 hpet_config;    /* configuration/cap */
0027         union {     /* timer compare register */
0028             u64 _hpet_hc64;
0029             u32 _hpet_hc32;
0030             unsigned long _hpet_compare;
0031         } _u1;
0032         u64 hpet_fsb[2];    /* FSB route */
0033     } hpet_timers[1];
0034 };
0035
0036 #define hpet_mc     _u0._hpet_mc
0037 #define hpet_compare    _u1._hpet_compare
0038
0039 #define HPET_MAX_TIMERS (32)
0040 #define HPET_MAX_IRQ    (32)
0041
0042 /*
0043  * HPET general capabilities register
0044  */
0045
0046 #define HPET_COUNTER_CLK_PERIOD_MASK    (0xffffffff00000000ULL)
0047 #define HPET_COUNTER_CLK_PERIOD_SHIFT   (32UL)
0048 #define HPET_VENDOR_ID_MASK     (0x00000000ffff0000ULL)
0049 #define HPET_VENDOR_ID_SHIFT        (16ULL)
0050 #define HPET_LEG_RT_CAP_MASK        (0x8000)
0051 #define HPET_COUNTER_SIZE_MASK      (0x2000)
0052 #define HPET_NUM_TIM_CAP_MASK       (0x1f00)
0053 #define HPET_NUM_TIM_CAP_SHIFT      (8ULL)
0054
0055 /*
0056  * HPET general configuration register
0057  */
0058
0059 #define HPET_LEG_RT_CNF_MASK        (2UL)
0060 #define HPET_ENABLE_CNF_MASK        (1UL)
0061
0062
0063 /*
0064  * Timer configuration register
0065  */
0066
0067 #define Tn_INT_ROUTE_CAP_MASK       (0xffffffff00000000ULL)
0068 #define Tn_INT_ROUTE_CAP_SHIFT      (32UL)
0069 #define Tn_FSB_INT_DELCAP_MASK      (0x8000UL)
0070 #define Tn_FSB_INT_DELCAP_SHIFT     (15)
0071 #define Tn_FSB_EN_CNF_MASK      (0x4000UL)
0072 #define Tn_FSB_EN_CNF_SHIFT     (14)
0073 #define Tn_INT_ROUTE_CNF_MASK       (0x3e00UL)
0074 #define Tn_INT_ROUTE_CNF_SHIFT      (9)
0075 #define Tn_32MODE_CNF_MASK      (0x0100UL)
0076 #define Tn_VAL_SET_CNF_MASK     (0x0040UL)
0077 #define Tn_SIZE_CAP_MASK        (0x0020UL)
0078 #define Tn_PER_INT_CAP_MASK     (0x0010UL)
0079 #define Tn_TYPE_CNF_MASK        (0x0008UL)
0080 #define Tn_INT_ENB_CNF_MASK     (0x0004UL)
0081 #define Tn_INT_TYPE_CNF_MASK        (0x0002UL)
0082
0083 /*
0084  * Timer FSB Interrupt Route Register
0085  */
0086
0087 #define Tn_FSB_INT_ADDR_MASK        (0xffffffff00000000ULL)
0088 #define Tn_FSB_INT_ADDR_SHIFT       (32UL)
0089 #define Tn_FSB_INT_VAL_MASK     (0x00000000ffffffffULL)
0090
0091 /*
0092  * exported interfaces
0093  */
0094
0095 struct hpet_data {
0096     unsigned long hd_phys_address;
0097     void __iomem *hd_address;
0098     unsigned short hd_nirqs;
0099     unsigned int hd_state;  /* timer allocated */
0100     unsigned int hd_irq[HPET_MAX_TIMERS];
0101 };
0102
0103 static inline void hpet_reserve_timer(struct hpet_data *hd, int timer)
0104 {
0105     hd->hd_state |= (1 << timer);
0106     return;
0107 }
0108
0109 int hpet_alloc(struct hpet_data *);
0110
0111 #endif              /* !__HPET__ */