include/linux/hisi_acc_qm.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* Copyright (c) 2019 HiSilicon Limited. */
0003 #ifndef HISI_ACC_QM_H
0004 #define HISI_ACC_QM_H
0005
0006 #include <linux/bitfield.h>
0007 #include <linux/debugfs.h>
0008 #include <linux/iopoll.h>
0009 #include <linux/module.h>
0010 #include <linux/pci.h>
0011
0012 #define QM_QNUM_V1          4096
0013 #define QM_QNUM_V2          1024
0014 #define QM_MAX_VFS_NUM_V2       63
0015
0016 /* qm user domain */
0017 #define QM_ARUSER_M_CFG_1       0x100088
0018 #define AXUSER_SNOOP_ENABLE     BIT(30)
0019 #define AXUSER_CMD_TYPE         GENMASK(14, 12)
0020 #define AXUSER_CMD_SMMU_NORMAL      1
0021 #define AXUSER_NS           BIT(6)
0022 #define AXUSER_NO           BIT(5)
0023 #define AXUSER_FP           BIT(4)
0024 #define AXUSER_SSV          BIT(0)
0025 #define AXUSER_BASE         (AXUSER_SNOOP_ENABLE |      \
0026                     FIELD_PREP(AXUSER_CMD_TYPE, \
0027                     AXUSER_CMD_SMMU_NORMAL) |   \
0028                     AXUSER_NS | AXUSER_NO | AXUSER_FP)
0029 #define QM_ARUSER_M_CFG_ENABLE      0x100090
0030 #define ARUSER_M_CFG_ENABLE     0xfffffffe
0031 #define QM_AWUSER_M_CFG_1       0x100098
0032 #define QM_AWUSER_M_CFG_ENABLE      0x1000a0
0033 #define AWUSER_M_CFG_ENABLE     0xfffffffe
0034 #define QM_WUSER_M_CFG_ENABLE       0x1000a8
0035 #define WUSER_M_CFG_ENABLE      0xffffffff
0036
0037 /* mailbox */
0038 #define QM_MB_CMD_SQC                   0x0
0039 #define QM_MB_CMD_CQC                   0x1
0040 #define QM_MB_CMD_EQC                   0x2
0041 #define QM_MB_CMD_AEQC                  0x3
0042 #define QM_MB_CMD_SQC_BT                0x4
0043 #define QM_MB_CMD_CQC_BT                0x5
0044 #define QM_MB_CMD_SQC_VFT_V2            0x6
0045 #define QM_MB_CMD_STOP_QP               0x8
0046 #define QM_MB_CMD_SRC                   0xc
0047 #define QM_MB_CMD_DST                   0xd
0048
0049 #define QM_MB_CMD_SEND_BASE     0x300
0050 #define QM_MB_EVENT_SHIFT               8
0051 #define QM_MB_BUSY_SHIFT        13
0052 #define QM_MB_OP_SHIFT          14
0053 #define QM_MB_CMD_DATA_ADDR_L       0x304
0054 #define QM_MB_CMD_DATA_ADDR_H       0x308
0055 #define QM_MB_MAX_WAIT_CNT      6000
0056
0057 /* doorbell */
0058 #define QM_DOORBELL_CMD_SQ              0
0059 #define QM_DOORBELL_CMD_CQ              1
0060 #define QM_DOORBELL_CMD_EQ              2
0061 #define QM_DOORBELL_CMD_AEQ             3
0062
0063 #define QM_DOORBELL_SQ_CQ_BASE_V2   0x1000
0064 #define QM_DOORBELL_EQ_AEQ_BASE_V2  0x2000
0065 #define QM_QP_MAX_NUM_SHIFT             11
0066 #define QM_DB_CMD_SHIFT_V2      12
0067 #define QM_DB_RAND_SHIFT_V2     16
0068 #define QM_DB_INDEX_SHIFT_V2        32
0069 #define QM_DB_PRIORITY_SHIFT_V2     48
0070 #define QM_VF_STATE         0x60
0071
0072 /* qm cache */
0073 #define QM_CACHE_CTL            0x100050
0074 #define SQC_CACHE_ENABLE        BIT(0)
0075 #define CQC_CACHE_ENABLE        BIT(1)
0076 #define SQC_CACHE_WB_ENABLE     BIT(4)
0077 #define SQC_CACHE_WB_THRD       GENMASK(10, 5)
0078 #define CQC_CACHE_WB_ENABLE     BIT(11)
0079 #define CQC_CACHE_WB_THRD       GENMASK(17, 12)
0080 #define QM_AXI_M_CFG            0x1000ac
0081 #define AXI_M_CFG           0xffff
0082 #define QM_AXI_M_CFG_ENABLE     0x1000b0
0083 #define AM_CFG_SINGLE_PORT_MAX_TRANS    0x300014
0084 #define AXI_M_CFG_ENABLE        0xffffffff
0085 #define QM_PEH_AXUSER_CFG       0x1000cc
0086 #define QM_PEH_AXUSER_CFG_ENABLE    0x1000d0
0087 #define PEH_AXUSER_CFG          0x401001
0088 #define PEH_AXUSER_CFG_ENABLE       0xffffffff
0089
0090 #define QM_AXI_RRESP            BIT(0)
0091 #define QM_AXI_BRESP            BIT(1)
0092 #define QM_ECC_MBIT         BIT(2)
0093 #define QM_ECC_1BIT         BIT(3)
0094 #define QM_ACC_GET_TASK_TIMEOUT     BIT(4)
0095 #define QM_ACC_DO_TASK_TIMEOUT      BIT(5)
0096 #define QM_ACC_WB_NOT_READY_TIMEOUT BIT(6)
0097 #define QM_SQ_CQ_VF_INVALID     BIT(7)
0098 #define QM_CQ_VF_INVALID        BIT(8)
0099 #define QM_SQ_VF_INVALID        BIT(9)
0100 #define QM_DB_TIMEOUT           BIT(10)
0101 #define QM_OF_FIFO_OF           BIT(11)
0102 #define QM_DB_RANDOM_INVALID        BIT(12)
0103 #define QM_MAILBOX_TIMEOUT      BIT(13)
0104 #define QM_FLR_TIMEOUT          BIT(14)
0105
0106 #define QM_BASE_NFE (QM_AXI_RRESP | QM_AXI_BRESP | QM_ECC_MBIT | \
0107              QM_ACC_GET_TASK_TIMEOUT | QM_DB_TIMEOUT | \
0108              QM_OF_FIFO_OF | QM_DB_RANDOM_INVALID | \
0109              QM_MAILBOX_TIMEOUT | QM_FLR_TIMEOUT)
0110 #define QM_BASE_CE          QM_ECC_1BIT
0111
0112 #define QM_Q_DEPTH          1024
0113 #define QM_MIN_QNUM                     2
0114 #define HISI_ACC_SGL_SGE_NR_MAX     255
0115 #define QM_SHAPER_CFG           0x100164
0116 #define QM_SHAPER_ENABLE        BIT(30)
0117 #define QM_SHAPER_TYPE1_OFFSET      10
0118
0119 /* page number for queue file region */
0120 #define QM_DOORBELL_PAGE_NR     1
0121
0122 /* uacce mode of the driver */
0123 #define UACCE_MODE_NOUACCE      0 /* don't use uacce */
0124 #define UACCE_MODE_SVA          1 /* use uacce sva mode */
0125 #define UACCE_MODE_DESC "0(default) means only register to crypto, 1 means both register to crypto and uacce"
0126
0127 enum qm_stop_reason {
0128     QM_NORMAL,
0129     QM_SOFT_RESET,
0130     QM_FLR,
0131 };
0132
0133 enum qm_state {
0134     QM_INIT = 0,
0135     QM_START,
0136     QM_CLOSE,
0137     QM_STOP,
0138 };
0139
0140 enum qp_state {
0141     QP_INIT = 1,
0142     QP_START,
0143     QP_STOP,
0144     QP_CLOSE,
0145 };
0146
0147 enum qm_hw_ver {
0148     QM_HW_UNKNOWN = -1,
0149     QM_HW_V1 = 0x20,
0150     QM_HW_V2 = 0x21,
0151     QM_HW_V3 = 0x30,
0152 };
0153
0154 enum qm_fun_type {
0155     QM_HW_PF,
0156     QM_HW_VF,
0157 };
0158
0159 enum qm_debug_file {
0160     CURRENT_QM,
0161     CURRENT_Q,
0162     CLEAR_ENABLE,
0163     DEBUG_FILE_NUM,
0164 };
0165
0166 enum qm_vf_state {
0167     QM_READY = 0,
0168     QM_NOT_READY,
0169 };
0170
0171 struct dfx_diff_registers {
0172     u32 *regs;
0173     u32 reg_offset;
0174     u32 reg_len;
0175 };
0176
0177 struct qm_dfx {
0178     atomic64_t err_irq_cnt;
0179     atomic64_t aeq_irq_cnt;
0180     atomic64_t abnormal_irq_cnt;
0181     atomic64_t create_qp_err_cnt;
0182     atomic64_t mb_err_cnt;
0183 };
0184
0185 struct debugfs_file {
0186     enum qm_debug_file index;
0187     struct mutex lock;
0188     struct qm_debug *debug;
0189 };
0190
0191 struct qm_debug {
0192     u32 curr_qm_qp_num;
0193     u32 sqe_mask_offset;
0194     u32 sqe_mask_len;
0195     struct qm_dfx dfx;
0196     struct dentry *debug_root;
0197     struct dentry *qm_d;
0198     struct debugfs_file files[DEBUG_FILE_NUM];
0199     unsigned int *qm_last_words;
0200     /* ACC engines recoreding last regs */
0201     unsigned int *last_words;
0202     struct dfx_diff_registers *qm_diff_regs;
0203     struct dfx_diff_registers *acc_diff_regs;
0204 };
0205
0206 struct qm_shaper_factor {
0207     u32 func_qos;
0208     u64 cir_b;
0209     u64 cir_u;
0210     u64 cir_s;
0211     u64 cbs_s;
0212 };
0213
0214 struct qm_dma {
0215     void *va;
0216     dma_addr_t dma;
0217     size_t size;
0218 };
0219
0220 struct hisi_qm_status {
0221     u32 eq_head;
0222     bool eqc_phase;
0223     u32 aeq_head;
0224     bool aeqc_phase;
0225     atomic_t flags;
0226     int stop_reason;
0227 };
0228
0229 struct hisi_qm;
0230
0231 struct hisi_qm_err_info {
0232     char *acpi_rst;
0233     u32 msi_wr_port;
0234     u32 ecc_2bits_mask;
0235     u32 dev_ce_mask;
0236     u32 ce;
0237     u32 nfe;
0238     u32 fe;
0239 };
0240
0241 struct hisi_qm_err_status {
0242     u32 is_qm_ecc_mbit;
0243     u32 is_dev_ecc_mbit;
0244 };
0245
0246 struct hisi_qm_err_ini {
0247     int (*hw_init)(struct hisi_qm *qm);
0248     void (*hw_err_enable)(struct hisi_qm *qm);
0249     void (*hw_err_disable)(struct hisi_qm *qm);
0250     u32 (*get_dev_hw_err_status)(struct hisi_qm *qm);
0251     void (*clear_dev_hw_err_status)(struct hisi_qm *qm, u32 err_sts);
0252     void (*open_axi_master_ooo)(struct hisi_qm *qm);
0253     void (*close_axi_master_ooo)(struct hisi_qm *qm);
0254     void (*open_sva_prefetch)(struct hisi_qm *qm);
0255     void (*close_sva_prefetch)(struct hisi_qm *qm);
0256     void (*log_dev_hw_err)(struct hisi_qm *qm, u32 err_sts);
0257     void (*show_last_dfx_regs)(struct hisi_qm *qm);
0258     void (*err_info_init)(struct hisi_qm *qm);
0259 };
0260
0261 struct hisi_qm_list {
0262     struct mutex lock;
0263     struct list_head list;
0264     int (*register_to_crypto)(struct hisi_qm *qm);
0265     void (*unregister_from_crypto)(struct hisi_qm *qm);
0266 };
0267
0268 struct hisi_qm_poll_data {
0269     struct hisi_qm *qm;
0270     struct work_struct work;
0271     u16 *qp_finish_id;
0272 };
0273
0274 struct hisi_qm {
0275     enum qm_hw_ver ver;
0276     enum qm_fun_type fun_type;
0277     const char *dev_name;
0278     struct pci_dev *pdev;
0279     void __iomem *io_base;
0280     void __iomem *db_io_base;
0281     u32 sqe_size;
0282     u32 qp_base;
0283     u32 qp_num;
0284     u32 qp_in_used;
0285     u32 ctrl_qp_num;
0286     u32 max_qp_num;
0287     u32 vfs_num;
0288     u32 db_interval;
0289     struct list_head list;
0290     struct hisi_qm_list *qm_list;
0291
0292     struct qm_dma qdma;
0293     struct qm_sqc *sqc;
0294     struct qm_cqc *cqc;
0295     struct qm_eqe *eqe;
0296     struct qm_aeqe *aeqe;
0297     dma_addr_t sqc_dma;
0298     dma_addr_t cqc_dma;
0299     dma_addr_t eqe_dma;
0300     dma_addr_t aeqe_dma;
0301
0302     struct hisi_qm_status status;
0303     const struct hisi_qm_err_ini *err_ini;
0304     struct hisi_qm_err_info err_info;
0305     struct hisi_qm_err_status err_status;
0306     unsigned long misc_ctl; /* driver removing and reset sched */
0307
0308     struct rw_semaphore qps_lock;
0309     struct idr qp_idr;
0310     struct hisi_qp *qp_array;
0311     struct hisi_qm_poll_data *poll_data;
0312
0313     struct mutex mailbox_lock;
0314
0315     const struct hisi_qm_hw_ops *ops;
0316
0317     struct qm_debug debug;
0318
0319     u32 error_mask;
0320
0321     struct workqueue_struct *wq;
0322     struct work_struct rst_work;
0323     struct work_struct cmd_process;
0324
0325     const char *algs;
0326     bool use_sva;
0327     bool is_frozen;
0328
0329     /* doorbell isolation enable */
0330     bool use_db_isolation;
0331     resource_size_t phys_base;
0332     resource_size_t db_phys_base;
0333     struct uacce_device *uacce;
0334     int mode;
0335     struct qm_shaper_factor *factor;
0336     u32 mb_qos;
0337     u32 type_rate;
0338 };
0339
0340 struct hisi_qp_status {
0341     atomic_t used;
0342     u16 sq_tail;
0343     u16 cq_head;
0344     bool cqc_phase;
0345     atomic_t flags;
0346 };
0347
0348 struct hisi_qp_ops {
0349     int (*fill_sqe)(void *sqe, void *q_parm, void *d_parm);
0350 };
0351
0352 struct hisi_qp {
0353     u32 qp_id;
0354     u8 alg_type;
0355     u8 req_type;
0356
0357     struct qm_dma qdma;
0358     void *sqe;
0359     struct qm_cqe *cqe;
0360     dma_addr_t sqe_dma;
0361     dma_addr_t cqe_dma;
0362
0363     struct hisi_qp_status qp_status;
0364     struct hisi_qp_ops *hw_ops;
0365     void *qp_ctx;
0366     void (*req_cb)(struct hisi_qp *qp, void *data);
0367     void (*event_cb)(struct hisi_qp *qp);
0368
0369     struct hisi_qm *qm;
0370     bool is_resetting;
0371     bool is_in_kernel;
0372     u16 pasid;
0373     struct uacce_queue *uacce_q;
0374 };
0375
0376 static inline int q_num_set(const char *val, const struct kernel_param *kp,
0377                 unsigned int device)
0378 {
0379     struct pci_dev *pdev = pci_get_device(PCI_VENDOR_ID_HUAWEI,
0380                           device, NULL);
0381     u32 n, q_num;
0382     int ret;
0383
0384     if (!val)
0385         return -EINVAL;
0386
0387     if (!pdev) {
0388         q_num = min_t(u32, QM_QNUM_V1, QM_QNUM_V2);
0389         pr_info("No device found currently, suppose queue number is %u\n",
0390             q_num);
0391     } else {
0392         if (pdev->revision == QM_HW_V1)
0393             q_num = QM_QNUM_V1;
0394         else
0395             q_num = QM_QNUM_V2;
0396     }
0397
0398     ret = kstrtou32(val, 10, &n);
0399     if (ret || n < QM_MIN_QNUM || n > q_num)
0400         return -EINVAL;
0401
0402     return param_set_int(val, kp);
0403 }
0404
0405 static inline int vfs_num_set(const char *val, const struct kernel_param *kp)
0406 {
0407     u32 n;
0408     int ret;
0409
0410     if (!val)
0411         return -EINVAL;
0412
0413     ret = kstrtou32(val, 10, &n);
0414     if (ret < 0)
0415         return ret;
0416
0417     if (n > QM_MAX_VFS_NUM_V2)
0418         return -EINVAL;
0419
0420     return param_set_int(val, kp);
0421 }
0422
0423 static inline int mode_set(const char *val, const struct kernel_param *kp)
0424 {
0425     u32 n;
0426     int ret;
0427
0428     if (!val)
0429         return -EINVAL;
0430
0431     ret = kstrtou32(val, 10, &n);
0432     if (ret != 0 || (n != UACCE_MODE_SVA &&
0433              n != UACCE_MODE_NOUACCE))
0434         return -EINVAL;
0435
0436     return param_set_int(val, kp);
0437 }
0438
0439 static inline int uacce_mode_set(const char *val, const struct kernel_param *kp)
0440 {
0441     return mode_set(val, kp);
0442 }
0443
0444 static inline void hisi_qm_init_list(struct hisi_qm_list *qm_list)
0445 {
0446     INIT_LIST_HEAD(&qm_list->list);
0447     mutex_init(&qm_list->lock);
0448 }
0449
0450 int hisi_qm_init(struct hisi_qm *qm);
0451 void hisi_qm_uninit(struct hisi_qm *qm);
0452 int hisi_qm_start(struct hisi_qm *qm);
0453 int hisi_qm_stop(struct hisi_qm *qm, enum qm_stop_reason r);
0454 int hisi_qm_start_qp(struct hisi_qp *qp, unsigned long arg);
0455 int hisi_qm_stop_qp(struct hisi_qp *qp);
0456 int hisi_qp_send(struct hisi_qp *qp, const void *msg);
0457 void hisi_qm_debug_init(struct hisi_qm *qm);
0458 void hisi_qm_debug_regs_clear(struct hisi_qm *qm);
0459 int hisi_qm_sriov_enable(struct pci_dev *pdev, int max_vfs);
0460 int hisi_qm_sriov_disable(struct pci_dev *pdev, bool is_frozen);
0461 int hisi_qm_sriov_configure(struct pci_dev *pdev, int num_vfs);
0462 void hisi_qm_dev_err_init(struct hisi_qm *qm);
0463 void hisi_qm_dev_err_uninit(struct hisi_qm *qm);
0464 int hisi_qm_diff_regs_init(struct hisi_qm *qm,
0465         struct dfx_diff_registers *dregs, int reg_len);
0466 void hisi_qm_diff_regs_uninit(struct hisi_qm *qm, int reg_len);
0467 void hisi_qm_acc_diff_regs_dump(struct hisi_qm *qm, struct seq_file *s,
0468         struct dfx_diff_registers *dregs, int regs_len);
0469
0470 pci_ers_result_t hisi_qm_dev_err_detected(struct pci_dev *pdev,
0471                       pci_channel_state_t state);
0472 pci_ers_result_t hisi_qm_dev_slot_reset(struct pci_dev *pdev);
0473 void hisi_qm_reset_prepare(struct pci_dev *pdev);
0474 void hisi_qm_reset_done(struct pci_dev *pdev);
0475
0476 int hisi_qm_wait_mb_ready(struct hisi_qm *qm);
0477 int hisi_qm_mb(struct hisi_qm *qm, u8 cmd, dma_addr_t dma_addr, u16 queue,
0478            bool op);
0479
0480 struct hisi_acc_sgl_pool;
0481 struct hisi_acc_hw_sgl *hisi_acc_sg_buf_map_to_hw_sgl(struct device *dev,
0482     struct scatterlist *sgl, struct hisi_acc_sgl_pool *pool,
0483     u32 index, dma_addr_t *hw_sgl_dma);
0484 void hisi_acc_sg_buf_unmap(struct device *dev, struct scatterlist *sgl,
0485                struct hisi_acc_hw_sgl *hw_sgl);
0486 struct hisi_acc_sgl_pool *hisi_acc_create_sgl_pool(struct device *dev,
0487                            u32 count, u32 sge_nr);
0488 void hisi_acc_free_sgl_pool(struct device *dev,
0489                 struct hisi_acc_sgl_pool *pool);
0490 int hisi_qm_alloc_qps_node(struct hisi_qm_list *qm_list, int qp_num,
0491                u8 alg_type, int node, struct hisi_qp **qps);
0492 void hisi_qm_free_qps(struct hisi_qp **qps, int qp_num);
0493 void hisi_qm_dev_shutdown(struct pci_dev *pdev);
0494 void hisi_qm_wait_task_finish(struct hisi_qm *qm, struct hisi_qm_list *qm_list);
0495 int hisi_qm_alg_register(struct hisi_qm *qm, struct hisi_qm_list *qm_list);
0496 void hisi_qm_alg_unregister(struct hisi_qm *qm, struct hisi_qm_list *qm_list);
0497 int hisi_qm_resume(struct device *dev);
0498 int hisi_qm_suspend(struct device *dev);
0499 void hisi_qm_pm_uninit(struct hisi_qm *qm);
0500 void hisi_qm_pm_init(struct hisi_qm *qm);
0501 int hisi_qm_get_dfx_access(struct hisi_qm *qm);
0502 void hisi_qm_put_dfx_access(struct hisi_qm *qm);
0503 void hisi_qm_regs_dump(struct seq_file *s, struct debugfs_regset32 *regset);
0504
0505 /* Used by VFIO ACC live migration driver */
0506 struct pci_driver *hisi_sec_get_pf_driver(void);
0507 struct pci_driver *hisi_hpre_get_pf_driver(void);
0508 struct pci_driver *hisi_zip_get_pf_driver(void);
0509 #endif