linux/gpio/driver.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef __LINUX_GPIO_DRIVER_H
0003 #define __LINUX_GPIO_DRIVER_H
0004
0005 #include <linux/device.h>
0006 #include <linux/irq.h>
0007 #include <linux/irqchip/chained_irq.h>
0008 #include <linux/irqdomain.h>
0009 #include <linux/lockdep.h>
0010 #include <linux/pinctrl/pinctrl.h>
0011 #include <linux/pinctrl/pinconf-generic.h>
0012 #include <linux/property.h>
0013 #include <linux/types.h>
0014
0015 #include <asm/msi.h>
0016
0017 struct gpio_desc;
0018 struct of_phandle_args;
0019 struct device_node;
0020 struct seq_file;
0021 struct gpio_device;
0022 struct module;
0023 enum gpiod_flags;
0024 enum gpio_lookup_flags;
0025
0026 struct gpio_chip;
0027
0028 union gpio_irq_fwspec {
0029     struct irq_fwspec   fwspec;
0030 #ifdef CONFIG_GENERIC_MSI_IRQ_DOMAIN
0031     msi_alloc_info_t    msiinfo;
0032 #endif
0033 };
0034
0035 #define GPIO_LINE_DIRECTION_IN  1
0036 #define GPIO_LINE_DIRECTION_OUT 0
0037
0038 /**
0039  * struct gpio_irq_chip - GPIO interrupt controller
0040  */
0041 struct gpio_irq_chip {
0042     /**
0043      * @chip:
0044      *
0045      * GPIO IRQ chip implementation, provided by GPIO driver.
0046      */
0047     struct irq_chip *chip;
0048
0049     /**
0050      * @domain:
0051      *
0052      * Interrupt translation domain; responsible for mapping between GPIO
0053      * hwirq number and Linux IRQ number.
0054      */
0055     struct irq_domain *domain;
0056
0057     /**
0058      * @domain_ops:
0059      *
0060      * Table of interrupt domain operations for this IRQ chip.
0061      */
0062     const struct irq_domain_ops *domain_ops;
0063
0064 #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
0065     /**
0066      * @fwnode:
0067      *
0068      * Firmware node corresponding to this gpiochip/irqchip, necessary
0069      * for hierarchical irqdomain support.
0070      */
0071     struct fwnode_handle *fwnode;
0072
0073     /**
0074      * @parent_domain:
0075      *
0076      * If non-NULL, will be set as the parent of this GPIO interrupt
0077      * controller's IRQ domain to establish a hierarchical interrupt
0078      * domain. The presence of this will activate the hierarchical
0079      * interrupt support.
0080      */
0081     struct irq_domain *parent_domain;
0082
0083     /**
0084      * @child_to_parent_hwirq:
0085      *
0086      * This callback translates a child hardware IRQ offset to a parent
0087      * hardware IRQ offset on a hierarchical interrupt chip. The child
0088      * hardware IRQs correspond to the GPIO index 0..ngpio-1 (see the
0089      * ngpio field of struct gpio_chip) and the corresponding parent
0090      * hardware IRQ and type (such as IRQ_TYPE_*) shall be returned by
0091      * the driver. The driver can calculate this from an offset or using
0092      * a lookup table or whatever method is best for this chip. Return
0093      * 0 on successful translation in the driver.
0094      *
0095      * If some ranges of hardware IRQs do not have a corresponding parent
0096      * HWIRQ, return -EINVAL, but also make sure to fill in @valid_mask and
0097      * @need_valid_mask to make these GPIO lines unavailable for
0098      * translation.
0099      */
0100     int (*child_to_parent_hwirq)(struct gpio_chip *gc,
0101                      unsigned int child_hwirq,
0102                      unsigned int child_type,
0103                      unsigned int *parent_hwirq,
0104                      unsigned int *parent_type);
0105
0106     /**
0107      * @populate_parent_alloc_arg :
0108      *
0109      * This optional callback allocates and populates the specific struct
0110      * for the parent's IRQ domain. If this is not specified, then
0111      * &gpiochip_populate_parent_fwspec_twocell will be used. A four-cell
0112      * variant named &gpiochip_populate_parent_fwspec_fourcell is also
0113      * available.
0114      */
0115     int (*populate_parent_alloc_arg)(struct gpio_chip *gc,
0116                      union gpio_irq_fwspec *fwspec,
0117                      unsigned int parent_hwirq,
0118                      unsigned int parent_type);
0119
0120     /**
0121      * @child_offset_to_irq:
0122      *
0123      * This optional callback is used to translate the child's GPIO line
0124      * offset on the GPIO chip to an IRQ number for the GPIO to_irq()
0125      * callback. If this is not specified, then a default callback will be
0126      * provided that returns the line offset.
0127      */
0128     unsigned int (*child_offset_to_irq)(struct gpio_chip *gc,
0129                         unsigned int pin);
0130
0131     /**
0132      * @child_irq_domain_ops:
0133      *
0134      * The IRQ domain operations that will be used for this GPIO IRQ
0135      * chip. If no operations are provided, then default callbacks will
0136      * be populated to setup the IRQ hierarchy. Some drivers need to
0137      * supply their own translate function.
0138      */
0139     struct irq_domain_ops child_irq_domain_ops;
0140 #endif
0141
0142     /**
0143      * @handler:
0144      *
0145      * The IRQ handler to use (often a predefined IRQ core function) for
0146      * GPIO IRQs, provided by GPIO driver.
0147      */
0148     irq_flow_handler_t handler;
0149
0150     /**
0151      * @default_type:
0152      *
0153      * Default IRQ triggering type applied during GPIO driver
0154      * initialization, provided by GPIO driver.
0155      */
0156     unsigned int default_type;
0157
0158     /**
0159      * @lock_key:
0160      *
0161      * Per GPIO IRQ chip lockdep class for IRQ lock.
0162      */
0163     struct lock_class_key *lock_key;
0164
0165     /**
0166      * @request_key:
0167      *
0168      * Per GPIO IRQ chip lockdep class for IRQ request.
0169      */
0170     struct lock_class_key *request_key;
0171
0172     /**
0173      * @parent_handler:
0174      *
0175      * The interrupt handler for the GPIO chip's parent interrupts, may be
0176      * NULL if the parent interrupts are nested rather than cascaded.
0177      */
0178     irq_flow_handler_t parent_handler;
0179
0180     union {
0181         /**
0182          * @parent_handler_data:
0183          *
0184          * If @per_parent_data is false, @parent_handler_data is a
0185          * single pointer used as the data associated with every
0186          * parent interrupt.
0187          */
0188         void *parent_handler_data;
0189
0190         /**
0191          * @parent_handler_data_array:
0192          *
0193          * If @per_parent_data is true, @parent_handler_data_array is
0194          * an array of @num_parents pointers, and is used to associate
0195          * different data for each parent. This cannot be NULL if
0196          * @per_parent_data is true.
0197          */
0198         void **parent_handler_data_array;
0199     };
0200
0201     /**
0202      * @num_parents:
0203      *
0204      * The number of interrupt parents of a GPIO chip.
0205      */
0206     unsigned int num_parents;
0207
0208     /**
0209      * @parents:
0210      *
0211      * A list of interrupt parents of a GPIO chip. This is owned by the
0212      * driver, so the core will only reference this list, not modify it.
0213      */
0214     unsigned int *parents;
0215
0216     /**
0217      * @map:
0218      *
0219      * A list of interrupt parents for each line of a GPIO chip.
0220      */
0221     unsigned int *map;
0222
0223     /**
0224      * @threaded:
0225      *
0226      * True if set the interrupt handling uses nested threads.
0227      */
0228     bool threaded;
0229
0230     /**
0231      * @per_parent_data:
0232      *
0233      * True if parent_handler_data_array describes a @num_parents
0234      * sized array to be used as parent data.
0235      */
0236     bool per_parent_data;
0237
0238     /**
0239      * @initialized:
0240      *
0241      * Flag to track GPIO chip irq member's initialization.
0242      * This flag will make sure GPIO chip irq members are not used
0243      * before they are initialized.
0244      */
0245     bool initialized;
0246
0247     /**
0248      * @init_hw: optional routine to initialize hardware before
0249      * an IRQ chip will be added. This is quite useful when
0250      * a particular driver wants to clear IRQ related registers
0251      * in order to avoid undesired events.
0252      */
0253     int (*init_hw)(struct gpio_chip *gc);
0254
0255     /**
0256      * @init_valid_mask: optional routine to initialize @valid_mask, to be
0257      * used if not all GPIO lines are valid interrupts. Sometimes some
0258      * lines just cannot fire interrupts, and this routine, when defined,
0259      * is passed a bitmap in "valid_mask" and it will have ngpios
0260      * bits from 0..(ngpios-1) set to "1" as in valid. The callback can
0261      * then directly set some bits to "0" if they cannot be used for
0262      * interrupts.
0263      */
0264     void (*init_valid_mask)(struct gpio_chip *gc,
0265                 unsigned long *valid_mask,
0266                 unsigned int ngpios);
0267
0268     /**
0269      * @valid_mask:
0270      *
0271      * If not %NULL, holds bitmask of GPIOs which are valid to be included
0272      * in IRQ domain of the chip.
0273      */
0274     unsigned long *valid_mask;
0275
0276     /**
0277      * @first:
0278      *
0279      * Required for static IRQ allocation. If set, irq_domain_add_simple()
0280      * will allocate and map all IRQs during initialization.
0281      */
0282     unsigned int first;
0283
0284     /**
0285      * @irq_enable:
0286      *
0287      * Store old irq_chip irq_enable callback
0288      */
0289     void        (*irq_enable)(struct irq_data *data);
0290
0291     /**
0292      * @irq_disable:
0293      *
0294      * Store old irq_chip irq_disable callback
0295      */
0296     void        (*irq_disable)(struct irq_data *data);
0297     /**
0298      * @irq_unmask:
0299      *
0300      * Store old irq_chip irq_unmask callback
0301      */
0302     void        (*irq_unmask)(struct irq_data *data);
0303
0304     /**
0305      * @irq_mask:
0306      *
0307      * Store old irq_chip irq_mask callback
0308      */
0309     void        (*irq_mask)(struct irq_data *data);
0310 };
0311
0312 /**
0313  * struct gpio_chip - abstract a GPIO controller
0314  * @label: a functional name for the GPIO device, such as a part
0315  *  number or the name of the SoC IP-block implementing it.
0316  * @gpiodev: the internal state holder, opaque struct
0317  * @parent: optional parent device providing the GPIOs
0318  * @fwnode: optional fwnode providing this controller's properties
0319  * @owner: helps prevent removal of modules exporting active GPIOs
0320  * @request: optional hook for chip-specific activation, such as
0321  *  enabling module power and clock; may sleep
0322  * @free: optional hook for chip-specific deactivation, such as
0323  *  disabling module power and clock; may sleep
0324  * @get_direction: returns direction for signal "offset", 0=out, 1=in,
0325  *  (same as GPIO_LINE_DIRECTION_OUT / GPIO_LINE_DIRECTION_IN),
0326  *  or negative error. It is recommended to always implement this
0327  *  function, even on input-only or output-only gpio chips.
0328  * @direction_input: configures signal "offset" as input, or returns error
0329  *  This can be omitted on input-only or output-only gpio chips.
0330  * @direction_output: configures signal "offset" as output, or returns error
0331  *  This can be omitted on input-only or output-only gpio chips.
0332  * @get: returns value for signal "offset", 0=low, 1=high, or negative error
0333  * @get_multiple: reads values for multiple signals defined by "mask" and
0334  *  stores them in "bits", returns 0 on success or negative error
0335  * @set: assigns output value for signal "offset"
0336  * @set_multiple: assigns output values for multiple signals defined by "mask"
0337  * @set_config: optional hook for all kinds of settings. Uses the same
0338  *  packed config format as generic pinconf.
0339  * @to_irq: optional hook supporting non-static gpio_to_irq() mappings;
0340  *  implementation may not sleep
0341  * @dbg_show: optional routine to show contents in debugfs; default code
0342  *  will be used when this is omitted, but custom code can show extra
0343  *  state (such as pullup/pulldown configuration).
0344  * @init_valid_mask: optional routine to initialize @valid_mask, to be used if
0345  *  not all GPIOs are valid.
0346  * @add_pin_ranges: optional routine to initialize pin ranges, to be used when
0347  *  requires special mapping of the pins that provides GPIO functionality.
0348  *  It is called after adding GPIO chip and before adding IRQ chip.
0349  * @en_hw_timestamp: Dependent on GPIO chip, an optional routine to
0350  *  enable hardware timestamp.
0351  * @dis_hw_timestamp: Dependent on GPIO chip, an optional routine to
0352  *  disable hardware timestamp.
0353  * @base: identifies the first GPIO number handled by this chip;
0354  *  or, if negative during registration, requests dynamic ID allocation.
0355  *  DEPRECATION: providing anything non-negative and nailing the base
0356  *  offset of GPIO chips is deprecated. Please pass -1 as base to
0357  *  let gpiolib select the chip base in all possible cases. We want to
0358  *  get rid of the static GPIO number space in the long run.
0359  * @ngpio: the number of GPIOs handled by this controller; the last GPIO
0360  *  handled is (base + ngpio - 1).
0361  * @offset: when multiple gpio chips belong to the same device this
0362  *  can be used as offset within the device so friendly names can
0363  *  be properly assigned.
0364  * @names: if set, must be an array of strings to use as alternative
0365  *      names for the GPIOs in this chip. Any entry in the array
0366  *      may be NULL if there is no alias for the GPIO, however the
0367  *      array must be @ngpio entries long.  A name can include a single printk
0368  *      format specifier for an unsigned int.  It is substituted by the actual
0369  *      number of the gpio.
0370  * @can_sleep: flag must be set iff get()/set() methods sleep, as they
0371  *  must while accessing GPIO expander chips over I2C or SPI. This
0372  *  implies that if the chip supports IRQs, these IRQs need to be threaded
0373  *  as the chip access may sleep when e.g. reading out the IRQ status
0374  *  registers.
0375  * @read_reg: reader function for generic GPIO
0376  * @write_reg: writer function for generic GPIO
0377  * @be_bits: if the generic GPIO has big endian bit order (bit 31 is representing
0378  *  line 0, bit 30 is line 1 ... bit 0 is line 31) this is set to true by the
0379  *  generic GPIO core. It is for internal housekeeping only.
0380  * @reg_dat: data (in) register for generic GPIO
0381  * @reg_set: output set register (out=high) for generic GPIO
0382  * @reg_clr: output clear register (out=low) for generic GPIO
0383  * @reg_dir_out: direction out setting register for generic GPIO
0384  * @reg_dir_in: direction in setting register for generic GPIO
0385  * @bgpio_dir_unreadable: indicates that the direction register(s) cannot
0386  *  be read and we need to rely on out internal state tracking.
0387  * @bgpio_bits: number of register bits used for a generic GPIO i.e.
0388  *  <register width> * 8
0389  * @bgpio_lock: used to lock chip->bgpio_data. Also, this is needed to keep
0390  *  shadowed and real data registers writes together.
0391  * @bgpio_data: shadowed data register for generic GPIO to clear/set bits
0392  *  safely.
0393  * @bgpio_dir: shadowed direction register for generic GPIO to clear/set
0394  *  direction safely. A "1" in this word means the line is set as
0395  *  output.
0396  *
0397  * A gpio_chip can help platforms abstract various sources of GPIOs so
0398  * they can all be accessed through a common programming interface.
0399  * Example sources would be SOC controllers, FPGAs, multifunction
0400  * chips, dedicated GPIO expanders, and so on.
0401  *
0402  * Each chip controls a number of signals, identified in method calls
0403  * by "offset" values in the range 0..(@ngpio - 1).  When those signals
0404  * are referenced through calls like gpio_get_value(gpio), the offset
0405  * is calculated by subtracting @base from the gpio number.
0406  */
0407 struct gpio_chip {
0408     const char      *label;
0409     struct gpio_device  *gpiodev;
0410     struct device       *parent;
0411     struct fwnode_handle    *fwnode;
0412     struct module       *owner;
0413
0414     int         (*request)(struct gpio_chip *gc,
0415                         unsigned int offset);
0416     void            (*free)(struct gpio_chip *gc,
0417                         unsigned int offset);
0418     int         (*get_direction)(struct gpio_chip *gc,
0419                         unsigned int offset);
0420     int         (*direction_input)(struct gpio_chip *gc,
0421                         unsigned int offset);
0422     int         (*direction_output)(struct gpio_chip *gc,
0423                         unsigned int offset, int value);
0424     int         (*get)(struct gpio_chip *gc,
0425                         unsigned int offset);
0426     int         (*get_multiple)(struct gpio_chip *gc,
0427                         unsigned long *mask,
0428                         unsigned long *bits);
0429     void            (*set)(struct gpio_chip *gc,
0430                         unsigned int offset, int value);
0431     void            (*set_multiple)(struct gpio_chip *gc,
0432                         unsigned long *mask,
0433                         unsigned long *bits);
0434     int         (*set_config)(struct gpio_chip *gc,
0435                           unsigned int offset,
0436                           unsigned long config);
0437     int         (*to_irq)(struct gpio_chip *gc,
0438                         unsigned int offset);
0439
0440     void            (*dbg_show)(struct seq_file *s,
0441                         struct gpio_chip *gc);
0442
0443     int         (*init_valid_mask)(struct gpio_chip *gc,
0444                            unsigned long *valid_mask,
0445                            unsigned int ngpios);
0446
0447     int         (*add_pin_ranges)(struct gpio_chip *gc);
0448
0449     int         (*en_hw_timestamp)(struct gpio_chip *gc,
0450                            u32 offset,
0451                            unsigned long flags);
0452     int         (*dis_hw_timestamp)(struct gpio_chip *gc,
0453                             u32 offset,
0454                             unsigned long flags);
0455     int         base;
0456     u16         ngpio;
0457     u16         offset;
0458     const char      *const *names;
0459     bool            can_sleep;
0460
0461 #if IS_ENABLED(CONFIG_GPIO_GENERIC)
0462     unsigned long (*read_reg)(void __iomem *reg);
0463     void (*write_reg)(void __iomem *reg, unsigned long data);
0464     bool be_bits;
0465     void __iomem *reg_dat;
0466     void __iomem *reg_set;
0467     void __iomem *reg_clr;
0468     void __iomem *reg_dir_out;
0469     void __iomem *reg_dir_in;
0470     bool bgpio_dir_unreadable;
0471     int bgpio_bits;
0472     raw_spinlock_t bgpio_lock;
0473     unsigned long bgpio_data;
0474     unsigned long bgpio_dir;
0475 #endif /* CONFIG_GPIO_GENERIC */
0476
0477 #ifdef CONFIG_GPIOLIB_IRQCHIP
0478     /*
0479      * With CONFIG_GPIOLIB_IRQCHIP we get an irqchip inside the gpiolib
0480      * to handle IRQs for most practical cases.
0481      */
0482
0483     /**
0484      * @irq:
0485      *
0486      * Integrates interrupt chip functionality with the GPIO chip. Can be
0487      * used to handle IRQs for most practical cases.
0488      */
0489     struct gpio_irq_chip irq;
0490 #endif /* CONFIG_GPIOLIB_IRQCHIP */
0491
0492     /**
0493      * @valid_mask:
0494      *
0495      * If not %NULL, holds bitmask of GPIOs which are valid to be used
0496      * from the chip.
0497      */
0498     unsigned long *valid_mask;
0499
0500 #if defined(CONFIG_OF_GPIO)
0501     /*
0502      * If CONFIG_OF_GPIO is enabled, then all GPIO controllers described in
0503      * the device tree automatically may have an OF translation
0504      */
0505
0506     /**
0507      * @of_node:
0508      *
0509      * Pointer to a device tree node representing this GPIO controller.
0510      */
0511     struct device_node *of_node;
0512
0513     /**
0514      * @of_gpio_n_cells:
0515      *
0516      * Number of cells used to form the GPIO specifier.
0517      */
0518     unsigned int of_gpio_n_cells;
0519
0520     /**
0521      * @of_xlate:
0522      *
0523      * Callback to translate a device tree GPIO specifier into a chip-
0524      * relative GPIO number and flags.
0525      */
0526     int (*of_xlate)(struct gpio_chip *gc,
0527             const struct of_phandle_args *gpiospec, u32 *flags);
0528
0529     /**
0530      * @of_gpio_ranges_fallback:
0531      *
0532      * Optional hook for the case that no gpio-ranges property is defined
0533      * within the device tree node "np" (usually DT before introduction
0534      * of gpio-ranges). So this callback is helpful to provide the
0535      * necessary backward compatibility for the pin ranges.
0536      */
0537     int (*of_gpio_ranges_fallback)(struct gpio_chip *gc,
0538                        struct device_node *np);
0539
0540 #endif /* CONFIG_OF_GPIO */
0541 };
0542
0543 extern const char *gpiochip_is_requested(struct gpio_chip *gc,
0544             unsigned int offset);
0545
0546 /**
0547  * for_each_requested_gpio_in_range - iterates over requested GPIOs in a given range
0548  * @chip:   the chip to query
0549  * @i:      loop variable
0550  * @base:   first GPIO in the range
0551  * @size:   amount of GPIOs to check starting from @base
0552  * @label:  label of current GPIO
0553  */
0554 #define for_each_requested_gpio_in_range(chip, i, base, size, label)            \
0555     for (i = 0; i < size; i++)                          \
0556         if ((label = gpiochip_is_requested(chip, base + i)) == NULL) {} else
0557
0558 /* Iterates over all requested GPIO of the given @chip */
0559 #define for_each_requested_gpio(chip, i, label)                     \
0560     for_each_requested_gpio_in_range(chip, i, 0, chip->ngpio, label)
0561
0562 /* add/remove chips */
0563 extern int gpiochip_add_data_with_key(struct gpio_chip *gc, void *data,
0564                       struct lock_class_key *lock_key,
0565                       struct lock_class_key *request_key);
0566
0567 /**
0568  * gpiochip_add_data() - register a gpio_chip
0569  * @gc: the chip to register, with gc->base initialized
0570  * @data: driver-private data associated with this chip
0571  *
0572  * Context: potentially before irqs will work
0573  *
0574  * When gpiochip_add_data() is called very early during boot, so that GPIOs
0575  * can be freely used, the gc->parent device must be registered before
0576  * the gpio framework's arch_initcall().  Otherwise sysfs initialization
0577  * for GPIOs will fail rudely.
0578  *
0579  * gpiochip_add_data() must only be called after gpiolib initialization,
0580  * i.e. after core_initcall().
0581  *
0582  * If gc->base is negative, this requests dynamic assignment of
0583  * a range of valid GPIOs.
0584  *
0585  * Returns:
0586  * A negative errno if the chip can't be registered, such as because the
0587  * gc->base is invalid or already associated with a different chip.
0588  * Otherwise it returns zero as a success code.
0589  */
0590 #ifdef CONFIG_LOCKDEP
0591 #define gpiochip_add_data(gc, data) ({      \
0592         static struct lock_class_key lock_key;  \
0593         static struct lock_class_key request_key;     \
0594         gpiochip_add_data_with_key(gc, data, &lock_key, \
0595                        &request_key);     \
0596     })
0597 #define devm_gpiochip_add_data(dev, gc, data) ({ \
0598         static struct lock_class_key lock_key;  \
0599         static struct lock_class_key request_key;     \
0600         devm_gpiochip_add_data_with_key(dev, gc, data, &lock_key, \
0601                        &request_key);     \
0602     })
0603 #else
0604 #define gpiochip_add_data(gc, data) gpiochip_add_data_with_key(gc, data, NULL, NULL)
0605 #define devm_gpiochip_add_data(dev, gc, data) \
0606     devm_gpiochip_add_data_with_key(dev, gc, data, NULL, NULL)
0607 #endif /* CONFIG_LOCKDEP */
0608
0609 static inline int gpiochip_add(struct gpio_chip *gc)
0610 {
0611     return gpiochip_add_data(gc, NULL);
0612 }
0613 extern void gpiochip_remove(struct gpio_chip *gc);
0614 extern int devm_gpiochip_add_data_with_key(struct device *dev, struct gpio_chip *gc, void *data,
0615                        struct lock_class_key *lock_key,
0616                        struct lock_class_key *request_key);
0617
0618 extern struct gpio_chip *gpiochip_find(void *data,
0619                   int (*match)(struct gpio_chip *gc, void *data));
0620
0621 bool gpiochip_line_is_irq(struct gpio_chip *gc, unsigned int offset);
0622 int gpiochip_reqres_irq(struct gpio_chip *gc, unsigned int offset);
0623 void gpiochip_relres_irq(struct gpio_chip *gc, unsigned int offset);
0624 void gpiochip_disable_irq(struct gpio_chip *gc, unsigned int offset);
0625 void gpiochip_enable_irq(struct gpio_chip *gc, unsigned int offset);
0626
0627 /* irq_data versions of the above */
0628 int gpiochip_irq_reqres(struct irq_data *data);
0629 void gpiochip_irq_relres(struct irq_data *data);
0630
0631 /* Paste this in your irq_chip structure  */
0632 #define GPIOCHIP_IRQ_RESOURCE_HELPERS                   \
0633         .irq_request_resources  = gpiochip_irq_reqres,      \
0634         .irq_release_resources  = gpiochip_irq_relres
0635
0636 static inline void gpio_irq_chip_set_chip(struct gpio_irq_chip *girq,
0637                       const struct irq_chip *chip)
0638 {
0639     /* Yes, dropping const is ugly, but it isn't like we have a choice */
0640     girq->chip = (struct irq_chip *)chip;
0641 }
0642
0643 /* Line status inquiry for drivers */
0644 bool gpiochip_line_is_open_drain(struct gpio_chip *gc, unsigned int offset);
0645 bool gpiochip_line_is_open_source(struct gpio_chip *gc, unsigned int offset);
0646
0647 /* Sleep persistence inquiry for drivers */
0648 bool gpiochip_line_is_persistent(struct gpio_chip *gc, unsigned int offset);
0649 bool gpiochip_line_is_valid(const struct gpio_chip *gc, unsigned int offset);
0650
0651 /* get driver data */
0652 void *gpiochip_get_data(struct gpio_chip *gc);
0653
0654 struct bgpio_pdata {
0655     const char *label;
0656     int base;
0657     int ngpio;
0658 };
0659
0660 #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
0661
0662 int gpiochip_populate_parent_fwspec_twocell(struct gpio_chip *gc,
0663                         union gpio_irq_fwspec *gfwspec,
0664                         unsigned int parent_hwirq,
0665                         unsigned int parent_type);
0666 int gpiochip_populate_parent_fwspec_fourcell(struct gpio_chip *gc,
0667                          union gpio_irq_fwspec *gfwspec,
0668                          unsigned int parent_hwirq,
0669                          unsigned int parent_type);
0670
0671 #endif /* CONFIG_IRQ_DOMAIN_HIERARCHY */
0672
0673 int bgpio_init(struct gpio_chip *gc, struct device *dev,
0674            unsigned long sz, void __iomem *dat, void __iomem *set,
0675            void __iomem *clr, void __iomem *dirout, void __iomem *dirin,
0676            unsigned long flags);
0677
0678 #define BGPIOF_BIG_ENDIAN       BIT(0)
0679 #define BGPIOF_UNREADABLE_REG_SET   BIT(1) /* reg_set is unreadable */
0680 #define BGPIOF_UNREADABLE_REG_DIR   BIT(2) /* reg_dir is unreadable */
0681 #define BGPIOF_BIG_ENDIAN_BYTE_ORDER    BIT(3)
0682 #define BGPIOF_READ_OUTPUT_REG_SET  BIT(4) /* reg_set stores output value */
0683 #define BGPIOF_NO_OUTPUT        BIT(5) /* only input */
0684 #define BGPIOF_NO_SET_ON_INPUT      BIT(6)
0685
0686 int gpiochip_irq_map(struct irq_domain *d, unsigned int irq,
0687              irq_hw_number_t hwirq);
0688 void gpiochip_irq_unmap(struct irq_domain *d, unsigned int irq);
0689
0690 int gpiochip_irq_domain_activate(struct irq_domain *domain,
0691                  struct irq_data *data, bool reserve);
0692 void gpiochip_irq_domain_deactivate(struct irq_domain *domain,
0693                     struct irq_data *data);
0694
0695 bool gpiochip_irqchip_irq_valid(const struct gpio_chip *gc,
0696                 unsigned int offset);
0697
0698 #ifdef CONFIG_GPIOLIB_IRQCHIP
0699 int gpiochip_irqchip_add_domain(struct gpio_chip *gc,
0700                 struct irq_domain *domain);
0701 #else
0702 static inline int gpiochip_irqchip_add_domain(struct gpio_chip *gc,
0703                           struct irq_domain *domain)
0704 {
0705     WARN_ON(1);
0706     return -EINVAL;
0707 }
0708 #endif
0709
0710 int gpiochip_generic_request(struct gpio_chip *gc, unsigned int offset);
0711 void gpiochip_generic_free(struct gpio_chip *gc, unsigned int offset);
0712 int gpiochip_generic_config(struct gpio_chip *gc, unsigned int offset,
0713                 unsigned long config);
0714
0715 /**
0716  * struct gpio_pin_range - pin range controlled by a gpio chip
0717  * @node: list for maintaining set of pin ranges, used internally
0718  * @pctldev: pinctrl device which handles corresponding pins
0719  * @range: actual range of pins controlled by a gpio controller
0720  */
0721 struct gpio_pin_range {
0722     struct list_head node;
0723     struct pinctrl_dev *pctldev;
0724     struct pinctrl_gpio_range range;
0725 };
0726
0727 #ifdef CONFIG_PINCTRL
0728
0729 int gpiochip_add_pin_range(struct gpio_chip *gc, const char *pinctl_name,
0730                unsigned int gpio_offset, unsigned int pin_offset,
0731                unsigned int npins);
0732 int gpiochip_add_pingroup_range(struct gpio_chip *gc,
0733             struct pinctrl_dev *pctldev,
0734             unsigned int gpio_offset, const char *pin_group);
0735 void gpiochip_remove_pin_ranges(struct gpio_chip *gc);
0736
0737 #else /* ! CONFIG_PINCTRL */
0738
0739 static inline int
0740 gpiochip_add_pin_range(struct gpio_chip *gc, const char *pinctl_name,
0741                unsigned int gpio_offset, unsigned int pin_offset,
0742                unsigned int npins)
0743 {
0744     return 0;
0745 }
0746 static inline int
0747 gpiochip_add_pingroup_range(struct gpio_chip *gc,
0748             struct pinctrl_dev *pctldev,
0749             unsigned int gpio_offset, const char *pin_group)
0750 {
0751     return 0;
0752 }
0753
0754 static inline void
0755 gpiochip_remove_pin_ranges(struct gpio_chip *gc)
0756 {
0757 }
0758
0759 #endif /* CONFIG_PINCTRL */
0760
0761 struct gpio_desc *gpiochip_request_own_desc(struct gpio_chip *gc,
0762                         unsigned int hwnum,
0763                         const char *label,
0764                         enum gpio_lookup_flags lflags,
0765                         enum gpiod_flags dflags);
0766 void gpiochip_free_own_desc(struct gpio_desc *desc);
0767
0768 #ifdef CONFIG_GPIOLIB
0769
0770 /* lock/unlock as IRQ */
0771 int gpiochip_lock_as_irq(struct gpio_chip *gc, unsigned int offset);
0772 void gpiochip_unlock_as_irq(struct gpio_chip *gc, unsigned int offset);
0773
0774
0775 struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc);
0776
0777 #else /* CONFIG_GPIOLIB */
0778
0779 static inline struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc)
0780 {
0781     /* GPIO can never have been requested */
0782     WARN_ON(1);
0783     return ERR_PTR(-ENODEV);
0784 }
0785
0786 static inline int gpiochip_lock_as_irq(struct gpio_chip *gc,
0787                        unsigned int offset)
0788 {
0789     WARN_ON(1);
0790     return -EINVAL;
0791 }
0792
0793 static inline void gpiochip_unlock_as_irq(struct gpio_chip *gc,
0794                       unsigned int offset)
0795 {
0796     WARN_ON(1);
0797 }
0798 #endif /* CONFIG_GPIOLIB */
0799
0800 #define for_each_gpiochip_node(dev, child)                  \
0801     device_for_each_child_node(dev, child)                  \
0802         if (!fwnode_property_present(child, "gpio-controller")) {} else
0803
0804 static inline unsigned int gpiochip_node_count(struct device *dev)
0805 {
0806     struct fwnode_handle *child;
0807     unsigned int count = 0;
0808
0809     for_each_gpiochip_node(dev, child)
0810         count++;
0811
0812     return count;
0813 }
0814
0815 static inline struct fwnode_handle *gpiochip_node_get_first(struct device *dev)
0816 {
0817     struct fwnode_handle *fwnode;
0818
0819     for_each_gpiochip_node(dev, fwnode)
0820         return fwnode;
0821
0822     return NULL;
0823 }
0824
0825 #endif /* __LINUX_GPIO_DRIVER_H */