include/linux/fsl_devices.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * include/linux/fsl_devices.h
0004  *
0005  * Definitions for any platform device related flags or structures for
0006  * Freescale processor devices
0007  *
0008  * Maintainer: Kumar Gala <galak@kernel.crashing.org>
0009  *
0010  * Copyright 2004,2012 Freescale Semiconductor, Inc
0011  */
0012
0013 #ifndef _FSL_DEVICE_H_
0014 #define _FSL_DEVICE_H_
0015
0016 #define FSL_UTMI_PHY_DLY    10  /*As per P1010RM, delay for UTMI
0017                 PHY CLK to become stable - 10ms*/
0018 #define FSL_USB_PHY_CLK_TIMEOUT 10000   /* uSec */
0019
0020 #include <linux/types.h>
0021
0022 /*
0023  * Some conventions on how we handle peripherals on Freescale chips
0024  *
0025  * unique device: a platform_device entry in fsl_plat_devs[] plus
0026  * associated device information in its platform_data structure.
0027  *
0028  * A chip is described by a set of unique devices.
0029  *
0030  * Each sub-arch has its own master list of unique devices and
0031  * enumerates them by enum fsl_devices in a sub-arch specific header
0032  *
0033  * The platform data structure is broken into two parts.  The
0034  * first is device specific information that help identify any
0035  * unique features of a peripheral.  The second is any
0036  * information that may be defined by the board or how the device
0037  * is connected externally of the chip.
0038  *
0039  * naming conventions:
0040  * - platform data structures: <driver>_platform_data
0041  * - platform data device flags: FSL_<driver>_DEV_<FLAG>
0042  * - platform data board flags: FSL_<driver>_BRD_<FLAG>
0043  *
0044  */
0045
0046 enum fsl_usb2_controller_ver {
0047     FSL_USB_VER_NONE = -1,
0048     FSL_USB_VER_OLD = 0,
0049     FSL_USB_VER_1_6 = 1,
0050     FSL_USB_VER_2_2 = 2,
0051     FSL_USB_VER_2_4 = 3,
0052     FSL_USB_VER_2_5 = 4,
0053 };
0054
0055 enum fsl_usb2_operating_modes {
0056     FSL_USB2_MPH_HOST,
0057     FSL_USB2_DR_HOST,
0058     FSL_USB2_DR_DEVICE,
0059     FSL_USB2_DR_OTG,
0060 };
0061
0062 enum fsl_usb2_phy_modes {
0063     FSL_USB2_PHY_NONE,
0064     FSL_USB2_PHY_ULPI,
0065     FSL_USB2_PHY_UTMI,
0066     FSL_USB2_PHY_UTMI_WIDE,
0067     FSL_USB2_PHY_SERIAL,
0068     FSL_USB2_PHY_UTMI_DUAL,
0069 };
0070
0071 struct clk;
0072 struct platform_device;
0073
0074 struct fsl_usb2_platform_data {
0075     /* board specific information */
0076     enum fsl_usb2_controller_ver    controller_ver;
0077     enum fsl_usb2_operating_modes   operating_mode;
0078     enum fsl_usb2_phy_modes     phy_mode;
0079     unsigned int            port_enables;
0080     unsigned int            workaround;
0081
0082     int     (*init)(struct platform_device *);
0083     void        (*exit)(struct platform_device *);
0084     void __iomem    *regs;      /* ioremap'd register base */
0085     struct clk  *clk;
0086     unsigned    power_budget;   /* hcd->power_budget */
0087     unsigned    big_endian_mmio:1;
0088     unsigned    big_endian_desc:1;
0089     unsigned    es:1;       /* need USBMODE:ES */
0090     unsigned    le_setup_buf:1;
0091     unsigned    have_sysif_regs:1;
0092     unsigned    invert_drvvbus:1;
0093     unsigned    invert_pwr_fault:1;
0094
0095     unsigned    suspended:1;
0096     unsigned    already_suspended:1;
0097     unsigned    has_fsl_erratum_a007792:1;
0098     unsigned    has_fsl_erratum_14:1;
0099     unsigned    has_fsl_erratum_a005275:1;
0100     unsigned    has_fsl_erratum_a005697:1;
0101     unsigned        has_fsl_erratum_a006918:1;
0102     unsigned    check_phy_clk_valid:1;
0103
0104     /* register save area for suspend/resume */
0105     u32     pm_command;
0106     u32     pm_status;
0107     u32     pm_intr_enable;
0108     u32     pm_frame_index;
0109     u32     pm_segment;
0110     u32     pm_frame_list;
0111     u32     pm_async_next;
0112     u32     pm_configured_flag;
0113     u32     pm_portsc;
0114     u32     pm_usbgenctrl;
0115 };
0116
0117 /* Flags in fsl_usb2_mph_platform_data */
0118 #define FSL_USB2_PORT0_ENABLED  0x00000001
0119 #define FSL_USB2_PORT1_ENABLED  0x00000002
0120
0121 #define FLS_USB2_WORKAROUND_ENGCM09152  (1 << 0)
0122
0123 struct spi_device;
0124
0125 struct fsl_spi_platform_data {
0126     u32     initial_spmode; /* initial SPMODE value */
0127     s16 bus_num;
0128     unsigned int flags;
0129 #define SPI_QE_CPU_MODE     (1 << 0) /* QE CPU ("PIO") mode */
0130 #define SPI_CPM_MODE        (1 << 1) /* CPM/QE ("DMA") mode */
0131 #define SPI_CPM1        (1 << 2) /* SPI unit is in CPM1 block */
0132 #define SPI_CPM2        (1 << 3) /* SPI unit is in CPM2 block */
0133 #define SPI_QE          (1 << 4) /* SPI unit is in QE block */
0134     /* board specific information */
0135     u16 max_chipselect;
0136     void    (*cs_control)(struct spi_device *spi, bool on);
0137     u32 sysclk;
0138 };
0139
0140 struct mpc8xx_pcmcia_ops {
0141     void(*hw_ctrl)(int slot, int enable);
0142     int(*voltage_set)(int slot, int vcc, int vpp);
0143 };
0144
0145 /* Returns non-zero if the current suspend operation would
0146  * lead to a deep sleep (i.e. power removed from the core,
0147  * instead of just the clock).
0148  */
0149 #if defined(CONFIG_PPC_83xx) && defined(CONFIG_SUSPEND)
0150 int fsl_deep_sleep(void);
0151 #else
0152 static inline int fsl_deep_sleep(void) { return 0; }
0153 #endif
0154
0155 #endif /* _FSL_DEVICE_H_ */