linux/fsl/ptp_qoriq.h

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (C) 2010 OMICRON electronics GmbH
0004  * Copyright 2018 NXP
0005  */
0006 #ifndef __PTP_QORIQ_H__
0007 #define __PTP_QORIQ_H__
0008
0009 #include <linux/io.h>
0010 #include <linux/interrupt.h>
0011 #include <linux/ptp_clock_kernel.h>
0012
0013 /*
0014  * qoriq ptp registers
0015  */
0016 struct ctrl_regs {
0017     u32 tmr_ctrl;     /* Timer control register */
0018     u32 tmr_tevent;   /* Timestamp event register */
0019     u32 tmr_temask;   /* Timer event mask register */
0020     u32 tmr_pevent;   /* Timestamp event register */
0021     u32 tmr_pemask;   /* Timer event mask register */
0022     u32 tmr_stat;     /* Timestamp status register */
0023     u32 tmr_cnt_h;    /* Timer counter high register */
0024     u32 tmr_cnt_l;    /* Timer counter low register */
0025     u32 tmr_add;      /* Timer drift compensation addend register */
0026     u32 tmr_acc;      /* Timer accumulator register */
0027     u32 tmr_prsc;     /* Timer prescale */
0028     u8  res1[4];
0029     u32 tmroff_h;     /* Timer offset high */
0030     u32 tmroff_l;     /* Timer offset low */
0031 };
0032
0033 struct alarm_regs {
0034     u32 tmr_alarm1_h; /* Timer alarm 1 high register */
0035     u32 tmr_alarm1_l; /* Timer alarm 1 high register */
0036     u32 tmr_alarm2_h; /* Timer alarm 2 high register */
0037     u32 tmr_alarm2_l; /* Timer alarm 2 high register */
0038 };
0039
0040 struct fiper_regs {
0041     u32 tmr_fiper1;   /* Timer fixed period interval */
0042     u32 tmr_fiper2;   /* Timer fixed period interval */
0043     u32 tmr_fiper3;   /* Timer fixed period interval */
0044 };
0045
0046 struct etts_regs {
0047     u32 tmr_etts1_h;  /* Timestamp of general purpose external trigger */
0048     u32 tmr_etts1_l;  /* Timestamp of general purpose external trigger */
0049     u32 tmr_etts2_h;  /* Timestamp of general purpose external trigger */
0050     u32 tmr_etts2_l;  /* Timestamp of general purpose external trigger */
0051 };
0052
0053 struct ptp_qoriq_registers {
0054     struct ctrl_regs __iomem *ctrl_regs;
0055     struct alarm_regs __iomem *alarm_regs;
0056     struct fiper_regs __iomem *fiper_regs;
0057     struct etts_regs __iomem *etts_regs;
0058 };
0059
0060 /* Offset definitions for the four register groups */
0061 #define ETSEC_CTRL_REGS_OFFSET  0x0
0062 #define ETSEC_ALARM_REGS_OFFSET 0x40
0063 #define ETSEC_FIPER_REGS_OFFSET 0x80
0064 #define ETSEC_ETTS_REGS_OFFSET  0xa0
0065
0066 #define CTRL_REGS_OFFSET    0x80
0067 #define ALARM_REGS_OFFSET   0xb8
0068 #define FIPER_REGS_OFFSET   0xd0
0069 #define ETTS_REGS_OFFSET    0xe0
0070
0071
0072 /* Bit definitions for the TMR_CTRL register */
0073 #define ALM1P                 (1<<31) /* Alarm1 output polarity */
0074 #define ALM2P                 (1<<30) /* Alarm2 output polarity */
0075 #define FIPERST               (1<<28) /* FIPER start indication */
0076 #define PP1L                  (1<<27) /* Fiper1 pulse loopback mode enabled. */
0077 #define PP2L                  (1<<26) /* Fiper2 pulse loopback mode enabled. */
0078 #define TCLK_PERIOD_SHIFT     (16) /* 1588 timer reference clock period. */
0079 #define TCLK_PERIOD_MASK      (0x3ff)
0080 #define RTPE                  (1<<15) /* Record Tx Timestamp to PAL Enable. */
0081 #define FRD                   (1<<14) /* FIPER Realignment Disable */
0082 #define ESFDP                 (1<<11) /* External Tx/Rx SFD Polarity. */
0083 #define ESFDE                 (1<<10) /* External Tx/Rx SFD Enable. */
0084 #define ETEP2                 (1<<9) /* External trigger 2 edge polarity */
0085 #define ETEP1                 (1<<8) /* External trigger 1 edge polarity */
0086 #define COPH                  (1<<7) /* Generated clock output phase. */
0087 #define CIPH                  (1<<6) /* External oscillator input clock phase */
0088 #define TMSR                  (1<<5) /* Timer soft reset. */
0089 #define BYP                   (1<<3) /* Bypass drift compensated clock */
0090 #define TE                    (1<<2) /* 1588 timer enable. */
0091 #define CKSEL_SHIFT           (0)    /* 1588 Timer reference clock source */
0092 #define CKSEL_MASK            (0x3)
0093
0094 /* Bit definitions for the TMR_TEVENT register */
0095 #define ETS2                  (1<<25) /* External trigger 2 timestamp sampled */
0096 #define ETS1                  (1<<24) /* External trigger 1 timestamp sampled */
0097 #define ALM2                  (1<<17) /* Current time = alarm time register 2 */
0098 #define ALM1                  (1<<16) /* Current time = alarm time register 1 */
0099 #define PP1                   (1<<7)  /* periodic pulse generated on FIPER1 */
0100 #define PP2                   (1<<6)  /* periodic pulse generated on FIPER2 */
0101 #define PP3                   (1<<5)  /* periodic pulse generated on FIPER3 */
0102
0103 /* Bit definitions for the TMR_TEMASK register */
0104 #define ETS2EN                (1<<25) /* External trigger 2 timestamp enable */
0105 #define ETS1EN                (1<<24) /* External trigger 1 timestamp enable */
0106 #define ALM2EN                (1<<17) /* Timer ALM2 event enable */
0107 #define ALM1EN                (1<<16) /* Timer ALM1 event enable */
0108 #define PP1EN                 (1<<7) /* Periodic pulse event 1 enable */
0109 #define PP2EN                 (1<<6) /* Periodic pulse event 2 enable */
0110
0111 /* Bit definitions for the TMR_PEVENT register */
0112 #define TXP2                  (1<<9) /* PTP transmitted timestamp im TXTS2 */
0113 #define TXP1                  (1<<8) /* PTP transmitted timestamp in TXTS1 */
0114 #define RXP                   (1<<0) /* PTP frame has been received */
0115
0116 /* Bit definitions for the TMR_PEMASK register */
0117 #define TXP2EN                (1<<9) /* Transmit PTP packet event 2 enable */
0118 #define TXP1EN                (1<<8) /* Transmit PTP packet event 1 enable */
0119 #define RXPEN                 (1<<0) /* Receive PTP packet event enable */
0120
0121 /* Bit definitions for the TMR_STAT register */
0122 #define STAT_VEC_SHIFT        (0) /* Timer general purpose status vector */
0123 #define STAT_VEC_MASK         (0x3f)
0124 #define ETS1_VLD              (1<<24)
0125 #define ETS2_VLD              (1<<25)
0126
0127 /* Bit definitions for the TMR_PRSC register */
0128 #define PRSC_OCK_SHIFT        (0) /* Output clock division/prescale factor. */
0129 #define PRSC_OCK_MASK         (0xffff)
0130
0131
0132 #define DRIVER      "ptp_qoriq"
0133 #define N_EXT_TS    2
0134
0135 #define DEFAULT_CKSEL       1
0136 #define DEFAULT_TMR_PRSC    2
0137 #define DEFAULT_FIPER1_PERIOD   1000000000
0138 #define DEFAULT_FIPER2_PERIOD   1000000000
0139 #define DEFAULT_FIPER3_PERIOD   1000000000
0140
0141 struct ptp_qoriq {
0142     void __iomem *base;
0143     struct ptp_qoriq_registers regs;
0144     spinlock_t lock; /* protects regs */
0145     struct ptp_clock *clock;
0146     struct ptp_clock_info caps;
0147     struct resource *rsrc;
0148     struct dentry *debugfs_root;
0149     struct device *dev;
0150     bool extts_fifo_support;
0151     bool fiper3_support;
0152     int irq;
0153     int phc_index;
0154     u32 tclk_period;  /* nanoseconds */
0155     u32 tmr_prsc;
0156     u32 tmr_add;
0157     u32 cksel;
0158     u32 tmr_fiper1;
0159     u32 tmr_fiper2;
0160     u32 tmr_fiper3;
0161     u32 (*read)(unsigned __iomem *addr);
0162     void (*write)(unsigned __iomem *addr, u32 val);
0163 };
0164
0165 static inline u32 qoriq_read_be(unsigned __iomem *addr)
0166 {
0167     return ioread32be(addr);
0168 }
0169
0170 static inline void qoriq_write_be(unsigned __iomem *addr, u32 val)
0171 {
0172     iowrite32be(val, addr);
0173 }
0174
0175 static inline u32 qoriq_read_le(unsigned __iomem *addr)
0176 {
0177     return ioread32(addr);
0178 }
0179
0180 static inline void qoriq_write_le(unsigned __iomem *addr, u32 val)
0181 {
0182     iowrite32(val, addr);
0183 }
0184
0185 irqreturn_t ptp_qoriq_isr(int irq, void *priv);
0186 int ptp_qoriq_init(struct ptp_qoriq *ptp_qoriq, void __iomem *base,
0187            const struct ptp_clock_info *caps);
0188 void ptp_qoriq_free(struct ptp_qoriq *ptp_qoriq);
0189 int ptp_qoriq_adjfine(struct ptp_clock_info *ptp, long scaled_ppm);
0190 int ptp_qoriq_adjtime(struct ptp_clock_info *ptp, s64 delta);
0191 int ptp_qoriq_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts);
0192 int ptp_qoriq_settime(struct ptp_clock_info *ptp,
0193               const struct timespec64 *ts);
0194 int ptp_qoriq_enable(struct ptp_clock_info *ptp,
0195              struct ptp_clock_request *rq, int on);
0196 int extts_clean_up(struct ptp_qoriq *ptp_qoriq, int index, bool update_event);
0197 #ifdef CONFIG_DEBUG_FS
0198 void ptp_qoriq_create_debugfs(struct ptp_qoriq *ptp_qoriq);
0199 void ptp_qoriq_remove_debugfs(struct ptp_qoriq *ptp_qoriq);
0200 #else
0201 static inline void ptp_qoriq_create_debugfs(struct ptp_qoriq *ptp_qoriq)
0202 { }
0203 static inline void ptp_qoriq_remove_debugfs(struct ptp_qoriq *ptp_qoriq)
0204 { }
0205 #endif
0206
0207 #endif