OSCL-LXR |
|
|
|
|||
0001 /* SPDX-License-Identifier: GPL-2.0-or-later */ 0002 /* 0003 * Freecale 85xx and 86xx Global Utilties register set 0004 * 0005 * Authors: Jeff Brown 0006 * Timur Tabi <timur@freescale.com> 0007 * 0008 * Copyright 2004,2007,2012 Freescale Semiconductor, Inc 0009 */ 0010 0011 #ifndef __FSL_GUTS_H__ 0012 #define __FSL_GUTS_H__ 0013 0014 #include <linux/types.h> 0015 #include <linux/io.h> 0016 0017 /* 0018 * Global Utility Registers. 0019 * 0020 * Not all registers defined in this structure are available on all chips, so 0021 * you are expected to know whether a given register actually exists on your 0022 * chip before you access it. 0023 * 0024 * Also, some registers are similar on different chips but have slightly 0025 * different names. In these cases, one name is chosen to avoid extraneous 0026 * #ifdefs. 0027 */ 0028 struct ccsr_guts { 0029 u32 porpllsr; /* 0x.0000 - POR PLL Ratio Status Register */ 0030 u32 porbmsr; /* 0x.0004 - POR Boot Mode Status Register */ 0031 u32 porimpscr; /* 0x.0008 - POR I/O Impedance Status and 0032 * Control Register 0033 */ 0034 u32 pordevsr; /* 0x.000c - POR I/O Device Status Register */ 0035 u32 pordbgmsr; /* 0x.0010 - POR Debug Mode Status Register */ 0036 u32 pordevsr2; /* 0x.0014 - POR device status register 2 */ 0037 u8 res018[0x20 - 0x18]; 0038 u32 porcir; /* 0x.0020 - POR Configuration Information 0039 * Register 0040 */ 0041 u8 res024[0x30 - 0x24]; 0042 u32 gpiocr; /* 0x.0030 - GPIO Control Register */ 0043 u8 res034[0x40 - 0x34]; 0044 u32 gpoutdr; /* 0x.0040 - General-Purpose Output Data 0045 * Register 0046 */ 0047 u8 res044[0x50 - 0x44]; 0048 u32 gpindr; /* 0x.0050 - General-Purpose Input Data 0049 * Register 0050 */ 0051 u8 res054[0x60 - 0x54]; 0052 u32 pmuxcr; /* 0x.0060 - Alternate Function Signal 0053 * Multiplex Control 0054 */ 0055 u32 pmuxcr2; /* 0x.0064 - Alternate function signal 0056 * multiplex control 2 0057 */ 0058 u32 dmuxcr; /* 0x.0068 - DMA Mux Control Register */ 0059 u8 res06c[0x70 - 0x6c]; 0060 u32 devdisr; /* 0x.0070 - Device Disable Control */ 0061 #define CCSR_GUTS_DEVDISR_TB1 0x00001000 0062 #define CCSR_GUTS_DEVDISR_TB0 0x00004000 0063 u32 devdisr2; /* 0x.0074 - Device Disable Control 2 */ 0064 u8 res078[0x7c - 0x78]; 0065 u32 pmjcr; /* 0x.007c - 4 Power Management Jog Control 0066 * Register 0067 */ 0068 u32 powmgtcsr; /* 0x.0080 - Power Management Status and 0069 * Control Register 0070 */ 0071 u32 pmrccr; /* 0x.0084 - Power Management Reset Counter 0072 * Configuration Register 0073 */ 0074 u32 pmpdccr; /* 0x.0088 - Power Management Power Down Counter 0075 * Configuration Register 0076 */ 0077 u32 pmcdr; /* 0x.008c - 4Power management clock disable 0078 * register 0079 */ 0080 u32 mcpsumr; /* 0x.0090 - Machine Check Summary Register */ 0081 u32 rstrscr; /* 0x.0094 - Reset Request Status and 0082 * Control Register 0083 */ 0084 u32 ectrstcr; /* 0x.0098 - Exception reset control register */ 0085 u32 autorstsr; /* 0x.009c - Automatic reset status register */ 0086 u32 pvr; /* 0x.00a0 - Processor Version Register */ 0087 u32 svr; /* 0x.00a4 - System Version Register */ 0088 u8 res0a8[0xb0 - 0xa8]; 0089 u32 rstcr; /* 0x.00b0 - Reset Control Register */ 0090 u8 res0b4[0xc0 - 0xb4]; 0091 u32 iovselsr; /* 0x.00c0 - I/O voltage select status register 0092 Called 'elbcvselcr' on 86xx SOCs */ 0093 u8 res0c4[0x100 - 0xc4]; 0094 u32 rcwsr[16]; /* 0x.0100 - Reset Control Word Status registers 0095 There are 16 registers */ 0096 u8 res140[0x224 - 0x140]; 0097 u32 iodelay1; /* 0x.0224 - IO delay control register 1 */ 0098 u32 iodelay2; /* 0x.0228 - IO delay control register 2 */ 0099 u8 res22c[0x604 - 0x22c]; 0100 u32 pamubypenr; /* 0x.604 - PAMU bypass enable register */ 0101 u8 res608[0x800 - 0x608]; 0102 u32 clkdvdr; /* 0x.0800 - Clock Divide Register */ 0103 u8 res804[0x900 - 0x804]; 0104 u32 ircr; /* 0x.0900 - Infrared Control Register */ 0105 u8 res904[0x908 - 0x904]; 0106 u32 dmacr; /* 0x.0908 - DMA Control Register */ 0107 u8 res90c[0x914 - 0x90c]; 0108 u32 elbccr; /* 0x.0914 - eLBC Control Register */ 0109 u8 res918[0xb20 - 0x918]; 0110 u32 ddr1clkdr; /* 0x.0b20 - DDR1 Clock Disable Register */ 0111 u32 ddr2clkdr; /* 0x.0b24 - DDR2 Clock Disable Register */ 0112 u32 ddrclkdr; /* 0x.0b28 - DDR Clock Disable Register */ 0113 u8 resb2c[0xe00 - 0xb2c]; 0114 u32 clkocr; /* 0x.0e00 - Clock Out Select Register */ 0115 u8 rese04[0xe10 - 0xe04]; 0116 u32 ddrdllcr; /* 0x.0e10 - DDR DLL Control Register */ 0117 u8 rese14[0xe20 - 0xe14]; 0118 u32 lbcdllcr; /* 0x.0e20 - LBC DLL Control Register */ 0119 u32 cpfor; /* 0x.0e24 - L2 charge pump fuse override 0120 * register 0121 */ 0122 u8 rese28[0xf04 - 0xe28]; 0123 u32 srds1cr0; /* 0x.0f04 - SerDes1 Control Register 0 */ 0124 u32 srds1cr1; /* 0x.0f08 - SerDes1 Control Register 0 */ 0125 u8 resf0c[0xf2c - 0xf0c]; 0126 u32 itcr; /* 0x.0f2c - Internal transaction control 0127 * register 0128 */ 0129 u8 resf30[0xf40 - 0xf30]; 0130 u32 srds2cr0; /* 0x.0f40 - SerDes2 Control Register 0 */ 0131 u32 srds2cr1; /* 0x.0f44 - SerDes2 Control Register 0 */ 0132 } __attribute__ ((packed)); 0133 0134 /* Alternate function signal multiplex control */ 0135 #define MPC85xx_PMUXCR_QE(x) (0x8000 >> (x)) 0136 0137 #ifdef CONFIG_PPC_86xx 0138 0139 #define CCSR_GUTS_DMACR_DEV_SSI 0 /* DMA controller/channel set to SSI */ 0140 #define CCSR_GUTS_DMACR_DEV_IR 1 /* DMA controller/channel set to IR */ 0141 0142 /* 0143 * Set the DMACR register in the GUTS 0144 * 0145 * The DMACR register determines the source of initiated transfers for each 0146 * channel on each DMA controller. Rather than have a bunch of repetitive 0147 * macros for the bit patterns, we just have a function that calculates 0148 * them. 0149 * 0150 * guts: Pointer to GUTS structure 0151 * co: The DMA controller (0 or 1) 0152 * ch: The channel on the DMA controller (0, 1, 2, or 3) 0153 * device: The device to set as the source (CCSR_GUTS_DMACR_DEV_xx) 0154 */ 0155 static inline void guts_set_dmacr(struct ccsr_guts __iomem *guts, 0156 unsigned int co, unsigned int ch, unsigned int device) 0157 { 0158 unsigned int shift = 16 + (8 * (1 - co) + 2 * (3 - ch)); 0159 0160 clrsetbits_be32(&guts->dmacr, 3 << shift, device << shift); 0161 } 0162 0163 #define CCSR_GUTS_PMUXCR_LDPSEL 0x00010000 0164 #define CCSR_GUTS_PMUXCR_SSI1_MASK 0x0000C000 /* Bitmask for SSI1 */ 0165 #define CCSR_GUTS_PMUXCR_SSI1_LA 0x00000000 /* Latched address */ 0166 #define CCSR_GUTS_PMUXCR_SSI1_HI 0x00004000 /* High impedance */ 0167 #define CCSR_GUTS_PMUXCR_SSI1_SSI 0x00008000 /* Used for SSI1 */ 0168 #define CCSR_GUTS_PMUXCR_SSI2_MASK 0x00003000 /* Bitmask for SSI2 */ 0169 #define CCSR_GUTS_PMUXCR_SSI2_LA 0x00000000 /* Latched address */ 0170 #define CCSR_GUTS_PMUXCR_SSI2_HI 0x00001000 /* High impedance */ 0171 #define CCSR_GUTS_PMUXCR_SSI2_SSI 0x00002000 /* Used for SSI2 */ 0172 #define CCSR_GUTS_PMUXCR_LA_22_25_LA 0x00000000 /* Latched Address */ 0173 #define CCSR_GUTS_PMUXCR_LA_22_25_HI 0x00000400 /* High impedance */ 0174 #define CCSR_GUTS_PMUXCR_DBGDRV 0x00000200 /* Signals not driven */ 0175 #define CCSR_GUTS_PMUXCR_DMA2_0 0x00000008 0176 #define CCSR_GUTS_PMUXCR_DMA2_3 0x00000004 0177 #define CCSR_GUTS_PMUXCR_DMA1_0 0x00000002 0178 #define CCSR_GUTS_PMUXCR_DMA1_3 0x00000001 0179 0180 /* 0181 * Set the DMA external control bits in the GUTS 0182 * 0183 * The DMA external control bits in the PMUXCR are only meaningful for 0184 * channels 0 and 3. Any other channels are ignored. 0185 * 0186 * guts: Pointer to GUTS structure 0187 * co: The DMA controller (0 or 1) 0188 * ch: The channel on the DMA controller (0, 1, 2, or 3) 0189 * value: the new value for the bit (0 or 1) 0190 */ 0191 static inline void guts_set_pmuxcr_dma(struct ccsr_guts __iomem *guts, 0192 unsigned int co, unsigned int ch, unsigned int value) 0193 { 0194 if ((ch == 0) || (ch == 3)) { 0195 unsigned int shift = 2 * (co + 1) - (ch & 1) - 1; 0196 0197 clrsetbits_be32(&guts->pmuxcr, 1 << shift, value << shift); 0198 } 0199 } 0200 0201 #define CCSR_GUTS_CLKDVDR_PXCKEN 0x80000000 0202 #define CCSR_GUTS_CLKDVDR_SSICKEN 0x20000000 0203 #define CCSR_GUTS_CLKDVDR_PXCKINV 0x10000000 0204 #define CCSR_GUTS_CLKDVDR_PXCKDLY_SHIFT 25 0205 #define CCSR_GUTS_CLKDVDR_PXCKDLY_MASK 0x06000000 0206 #define CCSR_GUTS_CLKDVDR_PXCKDLY(x) \ 0207 (((x) & 3) << CCSR_GUTS_CLKDVDR_PXCKDLY_SHIFT) 0208 #define CCSR_GUTS_CLKDVDR_PXCLK_SHIFT 16 0209 #define CCSR_GUTS_CLKDVDR_PXCLK_MASK 0x001F0000 0210 #define CCSR_GUTS_CLKDVDR_PXCLK(x) (((x) & 31) << CCSR_GUTS_CLKDVDR_PXCLK_SHIFT) 0211 #define CCSR_GUTS_CLKDVDR_SSICLK_MASK 0x000000FF 0212 #define CCSR_GUTS_CLKDVDR_SSICLK(x) ((x) & CCSR_GUTS_CLKDVDR_SSICLK_MASK) 0213 0214 #endif 0215 0216 struct ccsr_rcpm_v1 { 0217 u8 res0000[4]; 0218 __be32 cdozsr; /* 0x0004 Core Doze Status Register */ 0219 u8 res0008[4]; 0220 __be32 cdozcr; /* 0x000c Core Doze Control Register */ 0221 u8 res0010[4]; 0222 __be32 cnapsr; /* 0x0014 Core Nap Status Register */ 0223 u8 res0018[4]; 0224 __be32 cnapcr; /* 0x001c Core Nap Control Register */ 0225 u8 res0020[4]; 0226 __be32 cdozpsr; /* 0x0024 Core Doze Previous Status Register */ 0227 u8 res0028[4]; 0228 __be32 cnappsr; /* 0x002c Core Nap Previous Status Register */ 0229 u8 res0030[4]; 0230 __be32 cwaitsr; /* 0x0034 Core Wait Status Register */ 0231 u8 res0038[4]; 0232 __be32 cwdtdsr; /* 0x003c Core Watchdog Detect Status Register */ 0233 __be32 powmgtcsr; /* 0x0040 PM Control&Status Register */ 0234 #define RCPM_POWMGTCSR_SLP 0x00020000 0235 u8 res0044[12]; 0236 __be32 ippdexpcr; /* 0x0050 IP Powerdown Exception Control Register */ 0237 u8 res0054[16]; 0238 __be32 cpmimr; /* 0x0064 Core PM IRQ Mask Register */ 0239 u8 res0068[4]; 0240 __be32 cpmcimr; /* 0x006c Core PM Critical IRQ Mask Register */ 0241 u8 res0070[4]; 0242 __be32 cpmmcmr; /* 0x0074 Core PM Machine Check Mask Register */ 0243 u8 res0078[4]; 0244 __be32 cpmnmimr; /* 0x007c Core PM NMI Mask Register */ 0245 u8 res0080[4]; 0246 __be32 ctbenr; /* 0x0084 Core Time Base Enable Register */ 0247 u8 res0088[4]; 0248 __be32 ctbckselr; /* 0x008c Core Time Base Clock Select Register */ 0249 u8 res0090[4]; 0250 __be32 ctbhltcr; /* 0x0094 Core Time Base Halt Control Register */ 0251 u8 res0098[4]; 0252 __be32 cmcpmaskcr; /* 0x00a4 Core Machine Check Mask Register */ 0253 }; 0254 0255 struct ccsr_rcpm_v2 { 0256 u8 res_00[12]; 0257 __be32 tph10sr0; /* Thread PH10 Status Register */ 0258 u8 res_10[12]; 0259 __be32 tph10setr0; /* Thread PH10 Set Control Register */ 0260 u8 res_20[12]; 0261 __be32 tph10clrr0; /* Thread PH10 Clear Control Register */ 0262 u8 res_30[12]; 0263 __be32 tph10psr0; /* Thread PH10 Previous Status Register */ 0264 u8 res_40[12]; 0265 __be32 twaitsr0; /* Thread Wait Status Register */ 0266 u8 res_50[96]; 0267 __be32 pcph15sr; /* Physical Core PH15 Status Register */ 0268 __be32 pcph15setr; /* Physical Core PH15 Set Control Register */ 0269 __be32 pcph15clrr; /* Physical Core PH15 Clear Control Register */ 0270 __be32 pcph15psr; /* Physical Core PH15 Prev Status Register */ 0271 u8 res_c0[16]; 0272 __be32 pcph20sr; /* Physical Core PH20 Status Register */ 0273 __be32 pcph20setr; /* Physical Core PH20 Set Control Register */ 0274 __be32 pcph20clrr; /* Physical Core PH20 Clear Control Register */ 0275 __be32 pcph20psr; /* Physical Core PH20 Prev Status Register */ 0276 __be32 pcpw20sr; /* Physical Core PW20 Status Register */ 0277 u8 res_e0[12]; 0278 __be32 pcph30sr; /* Physical Core PH30 Status Register */ 0279 __be32 pcph30setr; /* Physical Core PH30 Set Control Register */ 0280 __be32 pcph30clrr; /* Physical Core PH30 Clear Control Register */ 0281 __be32 pcph30psr; /* Physical Core PH30 Prev Status Register */ 0282 u8 res_100[32]; 0283 __be32 ippwrgatecr; /* IP Power Gating Control Register */ 0284 u8 res_124[12]; 0285 __be32 powmgtcsr; /* Power Management Control & Status Reg */ 0286 #define RCPM_POWMGTCSR_LPM20_RQ 0x00100000 0287 #define RCPM_POWMGTCSR_LPM20_ST 0x00000200 0288 #define RCPM_POWMGTCSR_P_LPM20_ST 0x00000100 0289 u8 res_134[12]; 0290 __be32 ippdexpcr[4]; /* IP Powerdown Exception Control Reg */ 0291 u8 res_150[12]; 0292 __be32 tpmimr0; /* Thread PM Interrupt Mask Reg */ 0293 u8 res_160[12]; 0294 __be32 tpmcimr0; /* Thread PM Crit Interrupt Mask Reg */ 0295 u8 res_170[12]; 0296 __be32 tpmmcmr0; /* Thread PM Machine Check Interrupt Mask Reg */ 0297 u8 res_180[12]; 0298 __be32 tpmnmimr0; /* Thread PM NMI Mask Reg */ 0299 u8 res_190[12]; 0300 __be32 tmcpmaskcr0; /* Thread Machine Check Mask Control Reg */ 0301 __be32 pctbenr; /* Physical Core Time Base Enable Reg */ 0302 __be32 pctbclkselr; /* Physical Core Time Base Clock Select */ 0303 __be32 tbclkdivr; /* Time Base Clock Divider Register */ 0304 u8 res_1ac[4]; 0305 __be32 ttbhltcr[4]; /* Thread Time Base Halt Control Register */ 0306 __be32 clpcl10sr; /* Cluster PCL10 Status Register */ 0307 __be32 clpcl10setr; /* Cluster PCL30 Set Control Register */ 0308 __be32 clpcl10clrr; /* Cluster PCL30 Clear Control Register */ 0309 __be32 clpcl10psr; /* Cluster PCL30 Prev Status Register */ 0310 __be32 cddslpsetr; /* Core Domain Deep Sleep Set Register */ 0311 __be32 cddslpclrr; /* Core Domain Deep Sleep Clear Register */ 0312 __be32 cdpwroksetr; /* Core Domain Power OK Set Register */ 0313 __be32 cdpwrokclrr; /* Core Domain Power OK Clear Register */ 0314 __be32 cdpwrensr; /* Core Domain Power Enable Status Register */ 0315 __be32 cddslsr; /* Core Domain Deep Sleep Status Register */ 0316 u8 res_1e8[8]; 0317 __be32 dslpcntcr[8]; /* Deep Sleep Counter Cfg Register */ 0318 u8 res_300[3568]; 0319 }; 0320 0321 #endif
| [ Source navigation ] | [ Diff markup ] | [ Identifier search ] | [ general search ] |
|
This page was automatically generated by the 2.1.0 LXR engine. The LXR team |
|