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0001 // SPDX-License-Identifier: GPL-2.0
0002 #ifndef __FSL_FTM_H__
0003 #define __FSL_FTM_H__
0004 
0005 #define FTM_SC       0x0 /* Status And Control */
0006 #define FTM_CNT      0x4 /* Counter */
0007 #define FTM_MOD      0x8 /* Modulo */
0008 
0009 #define FTM_CNTIN    0x4C /* Counter Initial Value */
0010 #define FTM_STATUS   0x50 /* Capture And Compare Status */
0011 #define FTM_MODE     0x54 /* Features Mode Selection */
0012 #define FTM_SYNC     0x58 /* Synchronization */
0013 #define FTM_OUTINIT  0x5C /* Initial State For Channels Output */
0014 #define FTM_OUTMASK  0x60 /* Output Mask */
0015 #define FTM_COMBINE  0x64 /* Function For Linked Channels */
0016 #define FTM_DEADTIME 0x68 /* Deadtime Insertion Control */
0017 #define FTM_EXTTRIG  0x6C /* FTM External Trigger */
0018 #define FTM_POL      0x70 /* Channels Polarity */
0019 #define FTM_FMS      0x74 /* Fault Mode Status */
0020 #define FTM_FILTER   0x78 /* Input Capture Filter Control */
0021 #define FTM_FLTCTRL  0x7C /* Fault Control */
0022 #define FTM_QDCTRL   0x80 /* Quadrature Decoder Control And Status */
0023 #define FTM_CONF     0x84 /* Configuration */
0024 #define FTM_FLTPOL   0x88 /* FTM Fault Input Polarity */
0025 #define FTM_SYNCONF  0x8C /* Synchronization Configuration */
0026 #define FTM_INVCTRL  0x90 /* FTM Inverting Control */
0027 #define FTM_SWOCTRL  0x94 /* FTM Software Output Control */
0028 #define FTM_PWMLOAD  0x98 /* FTM PWM Load */
0029 
0030 #define FTM_SC_CLK_MASK_SHIFT   3
0031 #define FTM_SC_CLK_MASK     (3 << FTM_SC_CLK_MASK_SHIFT)
0032 #define FTM_SC_TOF      0x80
0033 #define FTM_SC_TOIE     0x40
0034 #define FTM_SC_CPWMS        0x20
0035 #define FTM_SC_CLKS     0x18
0036 #define FTM_SC_PS_1     0x0
0037 #define FTM_SC_PS_2     0x1
0038 #define FTM_SC_PS_4     0x2
0039 #define FTM_SC_PS_8     0x3
0040 #define FTM_SC_PS_16        0x4
0041 #define FTM_SC_PS_32        0x5
0042 #define FTM_SC_PS_64        0x6
0043 #define FTM_SC_PS_128       0x7
0044 #define FTM_SC_PS_MASK      0x7
0045 
0046 #define FTM_MODE_FAULTIE    0x80
0047 #define FTM_MODE_FAULTM     0x60
0048 #define FTM_MODE_CAPTEST    0x10
0049 #define FTM_MODE_PWMSYNC    0x8
0050 #define FTM_MODE_WPDIS      0x4
0051 #define FTM_MODE_INIT       0x2
0052 #define FTM_MODE_FTMEN      0x1
0053 
0054 /* NXP Errata: The PHAFLTREN and PHBFLTREN bits are tide to zero internally
0055  * and these bits cannot be set. Flextimer cannot use Filter in
0056  * Quadrature Decoder Mode.
0057  * https://community.nxp.com/thread/467648#comment-1010319
0058  */
0059 #define FTM_QDCTRL_PHAFLTREN    0x80
0060 #define FTM_QDCTRL_PHBFLTREN    0x40
0061 #define FTM_QDCTRL_PHAPOL   0x20
0062 #define FTM_QDCTRL_PHBPOL   0x10
0063 #define FTM_QDCTRL_QUADMODE 0x8
0064 #define FTM_QDCTRL_QUADDIR  0x4
0065 #define FTM_QDCTRL_TOFDIR   0x2
0066 #define FTM_QDCTRL_QUADEN   0x1
0067 
0068 #define FTM_FMS_FAULTF      0x80
0069 #define FTM_FMS_WPEN        0x40
0070 #define FTM_FMS_FAULTIN     0x10
0071 #define FTM_FMS_FAULTF3     0x8
0072 #define FTM_FMS_FAULTF2     0x4
0073 #define FTM_FMS_FAULTF1     0x2
0074 #define FTM_FMS_FAULTF0     0x1
0075 
0076 #define FTM_CSC_BASE        0xC
0077 #define FTM_CSC_MSB     0x20
0078 #define FTM_CSC_MSA     0x10
0079 #define FTM_CSC_ELSB        0x8
0080 #define FTM_CSC_ELSA        0x4
0081 #define FTM_CSC(_channel)   (FTM_CSC_BASE + ((_channel) * 8))
0082 
0083 #define FTM_CV_BASE     0x10
0084 #define FTM_CV(_channel)    (FTM_CV_BASE + ((_channel) * 8))
0085 
0086 #define FTM_PS_MAX      7
0087 
0088 #endif