linux/fsl/enetc_mdio.h

0001 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
0002 /* Copyright 2019 NXP */
0003
0004 #ifndef _FSL_ENETC_MDIO_H_
0005 #define _FSL_ENETC_MDIO_H_
0006
0007 #include <linux/phy.h>
0008
0009 /* PCS registers */
0010 #define ENETC_PCS_LINK_TIMER1           0x12
0011 #define ENETC_PCS_LINK_TIMER1_VAL       0x06a0
0012 #define ENETC_PCS_LINK_TIMER2           0x13
0013 #define ENETC_PCS_LINK_TIMER2_VAL       0x0003
0014 #define ENETC_PCS_IF_MODE           0x14
0015 #define ENETC_PCS_IF_MODE_SGMII_EN      BIT(0)
0016 #define ENETC_PCS_IF_MODE_USE_SGMII_AN      BIT(1)
0017 #define ENETC_PCS_IF_MODE_SGMII_SPEED(x)    (((x) << 2) & GENMASK(3, 2))
0018 #define ENETC_PCS_IF_MODE_DUPLEX_HALF       BIT(3)
0019
0020 /* Not a mistake, the SerDes PLL needs to be set at 3.125 GHz by Reset
0021  * Configuration Word (RCW, outside Linux control) for 2.5G SGMII mode. The PCS
0022  * still thinks it's at gigabit.
0023  */
0024 enum enetc_pcs_speed {
0025     ENETC_PCS_SPEED_10  = 0,
0026     ENETC_PCS_SPEED_100 = 1,
0027     ENETC_PCS_SPEED_1000    = 2,
0028     ENETC_PCS_SPEED_2500    = 2,
0029 };
0030
0031 struct enetc_hw;
0032
0033 struct enetc_mdio_priv {
0034     struct enetc_hw *hw;
0035     int mdio_base;
0036 };
0037
0038 #if IS_REACHABLE(CONFIG_FSL_ENETC_MDIO)
0039
0040 int enetc_mdio_read(struct mii_bus *bus, int phy_id, int regnum);
0041 int enetc_mdio_write(struct mii_bus *bus, int phy_id, int regnum, u16 value);
0042 struct enetc_hw *enetc_hw_alloc(struct device *dev, void __iomem *port_regs);
0043
0044 #else
0045
0046 static inline int enetc_mdio_read(struct mii_bus *bus, int phy_id, int regnum)
0047 { return -EINVAL; }
0048 static inline int enetc_mdio_write(struct mii_bus *bus, int phy_id, int regnum,
0049                    u16 value)
0050 { return -EINVAL; }
0051 struct enetc_hw *enetc_hw_alloc(struct device *dev, void __iomem *port_regs)
0052 { return ERR_PTR(-EINVAL); }
0053
0054 #endif
0055
0056 #endif