fsl/bestcomm/bestcomm_priv.h

0001 /*
0002  * Private header for the MPC52xx processor BestComm driver
0003  *
0004  * By private, we mean that driver should not use it directly. It's meant
0005  * to be used by the BestComm engine driver itself and by the intermediate
0006  * layer between the core and the drivers.
0007  *
0008  * Copyright (C) 2006      Sylvain Munaut <tnt@246tNt.com>
0009  * Copyright (C) 2005      Varma Electronics Oy,
0010  *                         ( by Andrey Volkov <avolkov@varma-el.com> )
0011  * Copyright (C) 2003-2004 MontaVista, Software, Inc.
0012  *                         ( by Dale Farnsworth <dfarnsworth@mvista.com> )
0013  *
0014  * This file is licensed under the terms of the GNU General Public License
0015  * version 2. This program is licensed "as is" without any warranty of any
0016  * kind, whether express or implied.
0017  */
0018
0019 #ifndef __BESTCOMM_PRIV_H__
0020 #define __BESTCOMM_PRIV_H__
0021
0022 #include <linux/spinlock.h>
0023 #include <linux/of.h>
0024 #include <asm/io.h>
0025 #include <asm/mpc52xx.h>
0026
0027 #include "sram.h"
0028
0029
0030 /* ======================================================================== */
0031 /* Engine related stuff                                                     */
0032 /* ======================================================================== */
0033
0034 /* Zones sizes and needed alignments */
0035 #define BCOM_MAX_TASKS      16
0036 #define BCOM_MAX_VAR        24
0037 #define BCOM_MAX_INC        8
0038 #define BCOM_MAX_FDT        64
0039 #define BCOM_MAX_CTX        20
0040 #define BCOM_CTX_SIZE       (BCOM_MAX_CTX * sizeof(u32))
0041 #define BCOM_CTX_ALIGN      0x100
0042 #define BCOM_VAR_SIZE       (BCOM_MAX_VAR * sizeof(u32))
0043 #define BCOM_INC_SIZE       (BCOM_MAX_INC * sizeof(u32))
0044 #define BCOM_VAR_ALIGN      0x80
0045 #define BCOM_FDT_SIZE       (BCOM_MAX_FDT * sizeof(u32))
0046 #define BCOM_FDT_ALIGN      0x100
0047
0048 /**
0049  * struct bcom_tdt - Task Descriptor Table Entry
0050  *
0051  */
0052 struct bcom_tdt {
0053     u32 start;
0054     u32 stop;
0055     u32 var;
0056     u32 fdt;
0057     u32 exec_status;    /* used internally by BestComm engine */
0058     u32 mvtp;       /* used internally by BestComm engine */
0059     u32 context;
0060     u32 litbase;
0061 };
0062
0063 /**
0064  * struct bcom_engine
0065  *
0066  * This holds all info needed globaly to handle the engine
0067  */
0068 struct bcom_engine {
0069     struct device_node      *ofnode;
0070     struct mpc52xx_sdma __iomem     *regs;
0071     phys_addr_t                      regs_base;
0072
0073     struct bcom_tdt         *tdt;
0074     u32             *ctx;
0075     u32             *var;
0076     u32             *fdt;
0077
0078     spinlock_t          lock;
0079 };
0080
0081 extern struct bcom_engine *bcom_eng;
0082
0083
0084 /* ======================================================================== */
0085 /* Tasks related stuff                                                      */
0086 /* ======================================================================== */
0087
0088 /* Tasks image header */
0089 #define BCOM_TASK_MAGIC     0x4243544B  /* 'BCTK' */
0090
0091 struct bcom_task_header {
0092     u32 magic;
0093     u8  desc_size;  /* the size fields     */
0094     u8  var_size;   /* are given in number */
0095     u8  inc_size;   /* of 32-bits words    */
0096     u8  first_var;
0097     u8  reserved[8];
0098 };
0099
0100 /* Descriptors structure & co */
0101 #define BCOM_DESC_NOP       0x000001f8
0102 #define BCOM_LCD_MASK       0x80000000
0103 #define BCOM_DRD_EXTENDED   0x40000000
0104 #define BCOM_DRD_INITIATOR_SHIFT    21
0105
0106 /* Tasks pragma */
0107 #define BCOM_PRAGMA_BIT_RSV     7   /* reserved pragma bit */
0108 #define BCOM_PRAGMA_BIT_PRECISE_INC 6   /* increment 0=when possible, */
0109                         /*           1=iter end */
0110 #define BCOM_PRAGMA_BIT_RST_ERROR_NO    5   /* don't reset errors on */
0111                         /* task enable */
0112 #define BCOM_PRAGMA_BIT_PACK        4   /* pack data enable */
0113 #define BCOM_PRAGMA_BIT_INTEGER     3   /* data alignment */
0114                         /* 0=frac(msb), 1=int(lsb) */
0115 #define BCOM_PRAGMA_BIT_SPECREAD    2   /* XLB speculative read */
0116 #define BCOM_PRAGMA_BIT_CW      1   /* write line buffer enable */
0117 #define BCOM_PRAGMA_BIT_RL      0   /* read line buffer enable */
0118
0119     /* Looks like XLB speculative read generates XLB errors when a buffer
0120      * is at the end of the physical memory. i.e. when accessing the
0121      * lasts words, the engine tries to prefetch the next but there is no
0122      * next ...
0123      */
0124 #define BCOM_STD_PRAGMA     ((0 << BCOM_PRAGMA_BIT_RSV)     | \
0125                  (0 << BCOM_PRAGMA_BIT_PRECISE_INC) | \
0126                  (0 << BCOM_PRAGMA_BIT_RST_ERROR_NO)    | \
0127                  (0 << BCOM_PRAGMA_BIT_PACK)        | \
0128                  (0 << BCOM_PRAGMA_BIT_INTEGER)     | \
0129                  (0 << BCOM_PRAGMA_BIT_SPECREAD)    | \
0130                  (1 << BCOM_PRAGMA_BIT_CW)      | \
0131                  (1 << BCOM_PRAGMA_BIT_RL))
0132
0133 #define BCOM_PCI_PRAGMA     ((0 << BCOM_PRAGMA_BIT_RSV)     | \
0134                  (0 << BCOM_PRAGMA_BIT_PRECISE_INC) | \
0135                  (0 << BCOM_PRAGMA_BIT_RST_ERROR_NO)    | \
0136                  (0 << BCOM_PRAGMA_BIT_PACK)        | \
0137                  (1 << BCOM_PRAGMA_BIT_INTEGER)     | \
0138                  (0 << BCOM_PRAGMA_BIT_SPECREAD)    | \
0139                  (1 << BCOM_PRAGMA_BIT_CW)      | \
0140                  (1 << BCOM_PRAGMA_BIT_RL))
0141
0142 #define BCOM_ATA_PRAGMA     BCOM_STD_PRAGMA
0143 #define BCOM_CRC16_DP_0_PRAGMA  BCOM_STD_PRAGMA
0144 #define BCOM_CRC16_DP_1_PRAGMA  BCOM_STD_PRAGMA
0145 #define BCOM_FEC_RX_BD_PRAGMA   BCOM_STD_PRAGMA
0146 #define BCOM_FEC_TX_BD_PRAGMA   BCOM_STD_PRAGMA
0147 #define BCOM_GEN_DP_0_PRAGMA    BCOM_STD_PRAGMA
0148 #define BCOM_GEN_DP_1_PRAGMA    BCOM_STD_PRAGMA
0149 #define BCOM_GEN_DP_2_PRAGMA    BCOM_STD_PRAGMA
0150 #define BCOM_GEN_DP_3_PRAGMA    BCOM_STD_PRAGMA
0151 #define BCOM_GEN_DP_BD_0_PRAGMA BCOM_STD_PRAGMA
0152 #define BCOM_GEN_DP_BD_1_PRAGMA BCOM_STD_PRAGMA
0153 #define BCOM_GEN_RX_BD_PRAGMA   BCOM_STD_PRAGMA
0154 #define BCOM_GEN_TX_BD_PRAGMA   BCOM_STD_PRAGMA
0155 #define BCOM_GEN_LPC_PRAGMA BCOM_STD_PRAGMA
0156 #define BCOM_PCI_RX_PRAGMA  BCOM_PCI_PRAGMA
0157 #define BCOM_PCI_TX_PRAGMA  BCOM_PCI_PRAGMA
0158
0159 /* Initiators number */
0160 #define BCOM_INITIATOR_ALWAYS    0
0161 #define BCOM_INITIATOR_SCTMR_0   1
0162 #define BCOM_INITIATOR_SCTMR_1   2
0163 #define BCOM_INITIATOR_FEC_RX    3
0164 #define BCOM_INITIATOR_FEC_TX    4
0165 #define BCOM_INITIATOR_ATA_RX    5
0166 #define BCOM_INITIATOR_ATA_TX    6
0167 #define BCOM_INITIATOR_SCPCI_RX  7
0168 #define BCOM_INITIATOR_SCPCI_TX  8
0169 #define BCOM_INITIATOR_PSC3_RX   9
0170 #define BCOM_INITIATOR_PSC3_TX  10
0171 #define BCOM_INITIATOR_PSC2_RX  11
0172 #define BCOM_INITIATOR_PSC2_TX  12
0173 #define BCOM_INITIATOR_PSC1_RX  13
0174 #define BCOM_INITIATOR_PSC1_TX  14
0175 #define BCOM_INITIATOR_SCTMR_2  15
0176 #define BCOM_INITIATOR_SCLPC    16
0177 #define BCOM_INITIATOR_PSC5_RX  17
0178 #define BCOM_INITIATOR_PSC5_TX  18
0179 #define BCOM_INITIATOR_PSC4_RX  19
0180 #define BCOM_INITIATOR_PSC4_TX  20
0181 #define BCOM_INITIATOR_I2C2_RX  21
0182 #define BCOM_INITIATOR_I2C2_TX  22
0183 #define BCOM_INITIATOR_I2C1_RX  23
0184 #define BCOM_INITIATOR_I2C1_TX  24
0185 #define BCOM_INITIATOR_PSC6_RX  25
0186 #define BCOM_INITIATOR_PSC6_TX  26
0187 #define BCOM_INITIATOR_IRDA_RX  25
0188 #define BCOM_INITIATOR_IRDA_TX  26
0189 #define BCOM_INITIATOR_SCTMR_3  27
0190 #define BCOM_INITIATOR_SCTMR_4  28
0191 #define BCOM_INITIATOR_SCTMR_5  29
0192 #define BCOM_INITIATOR_SCTMR_6  30
0193 #define BCOM_INITIATOR_SCTMR_7  31
0194
0195 /* Initiators priorities */
0196 #define BCOM_IPR_ALWAYS     7
0197 #define BCOM_IPR_SCTMR_0    2
0198 #define BCOM_IPR_SCTMR_1    2
0199 #define BCOM_IPR_FEC_RX     6
0200 #define BCOM_IPR_FEC_TX     5
0201 #define BCOM_IPR_ATA_RX     7
0202 #define BCOM_IPR_ATA_TX     7
0203 #define BCOM_IPR_SCPCI_RX   2
0204 #define BCOM_IPR_SCPCI_TX   2
0205 #define BCOM_IPR_PSC3_RX    2
0206 #define BCOM_IPR_PSC3_TX    2
0207 #define BCOM_IPR_PSC2_RX    2
0208 #define BCOM_IPR_PSC2_TX    2
0209 #define BCOM_IPR_PSC1_RX    2
0210 #define BCOM_IPR_PSC1_TX    2
0211 #define BCOM_IPR_SCTMR_2    2
0212 #define BCOM_IPR_SCLPC      2
0213 #define BCOM_IPR_PSC5_RX    2
0214 #define BCOM_IPR_PSC5_TX    2
0215 #define BCOM_IPR_PSC4_RX    2
0216 #define BCOM_IPR_PSC4_TX    2
0217 #define BCOM_IPR_I2C2_RX    2
0218 #define BCOM_IPR_I2C2_TX    2
0219 #define BCOM_IPR_I2C1_RX    2
0220 #define BCOM_IPR_I2C1_TX    2
0221 #define BCOM_IPR_PSC6_RX    2
0222 #define BCOM_IPR_PSC6_TX    2
0223 #define BCOM_IPR_IRDA_RX    2
0224 #define BCOM_IPR_IRDA_TX    2
0225 #define BCOM_IPR_SCTMR_3    2
0226 #define BCOM_IPR_SCTMR_4    2
0227 #define BCOM_IPR_SCTMR_5    2
0228 #define BCOM_IPR_SCTMR_6    2
0229 #define BCOM_IPR_SCTMR_7    2
0230
0231
0232 /* ======================================================================== */
0233 /* API                                                                      */
0234 /* ======================================================================== */
0235
0236 extern struct bcom_task *bcom_task_alloc(int bd_count, int bd_size, int priv_size);
0237 extern void bcom_task_free(struct bcom_task *tsk);
0238 extern int bcom_load_image(int task, u32 *task_image);
0239 extern void bcom_set_initiator(int task, int initiator);
0240
0241
0242 #define TASK_ENABLE             0x8000
0243
0244 /**
0245  * bcom_disable_prefetch - Hook to disable bus prefetching
0246  *
0247  * ATA DMA and the original MPC5200 need this due to silicon bugs.  At the
0248  * moment disabling prefetch is a one-way street.  There is no mechanism
0249  * in place to turn prefetch back on after it has been disabled.  There is
0250  * no reason it couldn't be done, it would just be more complex to implement.
0251  */
0252 static inline void bcom_disable_prefetch(void)
0253 {
0254     u16 regval;
0255
0256     regval = in_be16(&bcom_eng->regs->PtdCntrl);
0257     out_be16(&bcom_eng->regs->PtdCntrl, regval | 1);
0258 };
0259
0260 static inline void
0261 bcom_enable_task(int task)
0262 {
0263         u16 reg;
0264         reg = in_be16(&bcom_eng->regs->tcr[task]);
0265         out_be16(&bcom_eng->regs->tcr[task],  reg | TASK_ENABLE);
0266 }
0267
0268 static inline void
0269 bcom_disable_task(int task)
0270 {
0271         u16 reg = in_be16(&bcom_eng->regs->tcr[task]);
0272         out_be16(&bcom_eng->regs->tcr[task], reg & ~TASK_ENABLE);
0273 }
0274
0275
0276 static inline u32 *
0277 bcom_task_desc(int task)
0278 {
0279     return bcom_sram_pa2va(bcom_eng->tdt[task].start);
0280 }
0281
0282 static inline int
0283 bcom_task_num_descs(int task)
0284 {
0285     return (bcom_eng->tdt[task].stop - bcom_eng->tdt[task].start)/sizeof(u32) + 1;
0286 }
0287
0288 static inline u32 *
0289 bcom_task_var(int task)
0290 {
0291     return bcom_sram_pa2va(bcom_eng->tdt[task].var);
0292 }
0293
0294 static inline u32 *
0295 bcom_task_inc(int task)
0296 {
0297     return &bcom_task_var(task)[BCOM_MAX_VAR];
0298 }
0299
0300
0301 static inline int
0302 bcom_drd_is_extended(u32 desc)
0303 {
0304     return (desc) & BCOM_DRD_EXTENDED;
0305 }
0306
0307 static inline int
0308 bcom_desc_is_drd(u32 desc)
0309 {
0310     return !(desc & BCOM_LCD_MASK) && desc != BCOM_DESC_NOP;
0311 }
0312
0313 static inline int
0314 bcom_desc_initiator(u32 desc)
0315 {
0316     return (desc >> BCOM_DRD_INITIATOR_SHIFT) & 0x1f;
0317 }
0318
0319 static inline void
0320 bcom_set_desc_initiator(u32 *desc, int initiator)
0321 {
0322     *desc = (*desc & ~(0x1f << BCOM_DRD_INITIATOR_SHIFT)) |
0323             ((initiator & 0x1f) << BCOM_DRD_INITIATOR_SHIFT);
0324 }
0325
0326
0327 static inline void
0328 bcom_set_task_pragma(int task, int pragma)
0329 {
0330     u32 *fdt = &bcom_eng->tdt[task].fdt;
0331     *fdt = (*fdt & ~0xff) | pragma;
0332 }
0333
0334 static inline void
0335 bcom_set_task_auto_start(int task, int next_task)
0336 {
0337     u16 __iomem *tcr = &bcom_eng->regs->tcr[task];
0338     out_be16(tcr, (in_be16(tcr) & ~0xff) | 0x00c0 | next_task);
0339 }
0340
0341 static inline void
0342 bcom_set_tcr_initiator(int task, int initiator)
0343 {
0344     u16 __iomem *tcr = &bcom_eng->regs->tcr[task];
0345     out_be16(tcr, (in_be16(tcr) & ~0x1f00) | ((initiator & 0x1f) << 8));
0346 }
0347
0348
0349 #endif /* __BESTCOMM_PRIV_H__ */
0350