Back to home page

OSCL-LXR
 
 

     

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Xilinx Zynq MPSoC Firmware layer
0004  *
0005  *  Copyright (C) 2014-2021 Xilinx
0006  *
0007  *  Michal Simek <michal.simek@xilinx.com>
0008  *  Davorin Mista <davorin.mista@aggios.com>
0009  *  Jolly Shah <jollys@xilinx.com>
0010  *  Rajan Vaja <rajanv@xilinx.com>
0011  */
0012 
0013 #ifndef __FIRMWARE_ZYNQMP_H__
0014 #define __FIRMWARE_ZYNQMP_H__
0015 
0016 #include <linux/err.h>
0017 
0018 #define ZYNQMP_PM_VERSION_MAJOR 1
0019 #define ZYNQMP_PM_VERSION_MINOR 0
0020 
0021 #define ZYNQMP_PM_VERSION   ((ZYNQMP_PM_VERSION_MAJOR << 16) | \
0022                     ZYNQMP_PM_VERSION_MINOR)
0023 
0024 #define ZYNQMP_TZ_VERSION_MAJOR 1
0025 #define ZYNQMP_TZ_VERSION_MINOR 0
0026 
0027 #define ZYNQMP_TZ_VERSION   ((ZYNQMP_TZ_VERSION_MAJOR << 16) | \
0028                     ZYNQMP_TZ_VERSION_MINOR)
0029 
0030 /* SMC SIP service Call Function Identifier Prefix */
0031 #define PM_SIP_SVC          0xC2000000
0032 
0033 /* PM API versions */
0034 #define PM_API_VERSION_2    2
0035 
0036 /* ATF only commands */
0037 #define TF_A_PM_REGISTER_SGI        0xa04
0038 #define PM_GET_TRUSTZONE_VERSION    0xa03
0039 #define PM_SET_SUSPEND_MODE     0xa02
0040 #define GET_CALLBACK_DATA       0xa01
0041 
0042 /* Number of 32bits values in payload */
0043 #define PAYLOAD_ARG_CNT 4U
0044 
0045 /* Number of arguments for a callback */
0046 #define CB_ARG_CNT     4
0047 
0048 /* Payload size (consists of callback API ID + arguments) */
0049 #define CB_PAYLOAD_SIZE (CB_ARG_CNT + 1)
0050 
0051 #define ZYNQMP_PM_MAX_QOS       100U
0052 
0053 #define GSS_NUM_REGS    (4)
0054 
0055 /* Node capabilities */
0056 #define ZYNQMP_PM_CAPABILITY_ACCESS 0x1U
0057 #define ZYNQMP_PM_CAPABILITY_CONTEXT    0x2U
0058 #define ZYNQMP_PM_CAPABILITY_WAKEUP 0x4U
0059 #define ZYNQMP_PM_CAPABILITY_UNUSABLE   0x8U
0060 
0061 /* Loader commands */
0062 #define PM_LOAD_PDI 0x701
0063 #define PDI_SRC_DDR 0xF
0064 
0065 /*
0066  * Firmware FPGA Manager flags
0067  * XILINX_ZYNQMP_PM_FPGA_FULL:  FPGA full reconfiguration
0068  * XILINX_ZYNQMP_PM_FPGA_PARTIAL: FPGA partial reconfiguration
0069  */
0070 #define XILINX_ZYNQMP_PM_FPGA_FULL  0x0U
0071 #define XILINX_ZYNQMP_PM_FPGA_PARTIAL   BIT(0)
0072 
0073 /*
0074  * Node IDs for the Error Events.
0075  */
0076 #define EVENT_ERROR_PMC_ERR1    (0x28100000U)
0077 #define EVENT_ERROR_PMC_ERR2    (0x28104000U)
0078 #define EVENT_ERROR_PSM_ERR1    (0x28108000U)
0079 #define EVENT_ERROR_PSM_ERR2    (0x2810C000U)
0080 
0081 enum pm_api_cb_id {
0082     PM_INIT_SUSPEND_CB = 30,
0083     PM_ACKNOWLEDGE_CB = 31,
0084     PM_NOTIFY_CB = 32,
0085 };
0086 
0087 enum pm_api_id {
0088     PM_GET_API_VERSION = 1,
0089     PM_REGISTER_NOTIFIER = 5,
0090     PM_SYSTEM_SHUTDOWN = 12,
0091     PM_REQUEST_NODE = 13,
0092     PM_RELEASE_NODE = 14,
0093     PM_SET_REQUIREMENT = 15,
0094     PM_RESET_ASSERT = 17,
0095     PM_RESET_GET_STATUS = 18,
0096     PM_MMIO_WRITE = 19,
0097     PM_MMIO_READ = 20,
0098     PM_PM_INIT_FINALIZE = 21,
0099     PM_FPGA_LOAD = 22,
0100     PM_FPGA_GET_STATUS = 23,
0101     PM_GET_CHIPID = 24,
0102     PM_SECURE_SHA = 26,
0103     PM_PINCTRL_REQUEST = 28,
0104     PM_PINCTRL_RELEASE = 29,
0105     PM_PINCTRL_GET_FUNCTION = 30,
0106     PM_PINCTRL_SET_FUNCTION = 31,
0107     PM_PINCTRL_CONFIG_PARAM_GET = 32,
0108     PM_PINCTRL_CONFIG_PARAM_SET = 33,
0109     PM_IOCTL = 34,
0110     PM_QUERY_DATA = 35,
0111     PM_CLOCK_ENABLE = 36,
0112     PM_CLOCK_DISABLE = 37,
0113     PM_CLOCK_GETSTATE = 38,
0114     PM_CLOCK_SETDIVIDER = 39,
0115     PM_CLOCK_GETDIVIDER = 40,
0116     PM_CLOCK_SETRATE = 41,
0117     PM_CLOCK_GETRATE = 42,
0118     PM_CLOCK_SETPARENT = 43,
0119     PM_CLOCK_GETPARENT = 44,
0120     PM_SECURE_AES = 47,
0121     PM_FEATURE_CHECK = 63,
0122 };
0123 
0124 /* PMU-FW return status codes */
0125 enum pm_ret_status {
0126     XST_PM_SUCCESS = 0,
0127     XST_PM_NO_FEATURE = 19,
0128     XST_PM_INTERNAL = 2000,
0129     XST_PM_CONFLICT = 2001,
0130     XST_PM_NO_ACCESS = 2002,
0131     XST_PM_INVALID_NODE = 2003,
0132     XST_PM_DOUBLE_REQ = 2004,
0133     XST_PM_ABORT_SUSPEND = 2005,
0134     XST_PM_MULT_USER = 2008,
0135 };
0136 
0137 enum pm_ioctl_id {
0138     IOCTL_SD_DLL_RESET = 6,
0139     IOCTL_SET_SD_TAPDELAY = 7,
0140     IOCTL_SET_PLL_FRAC_MODE = 8,
0141     IOCTL_GET_PLL_FRAC_MODE = 9,
0142     IOCTL_SET_PLL_FRAC_DATA = 10,
0143     IOCTL_GET_PLL_FRAC_DATA = 11,
0144     IOCTL_WRITE_GGS = 12,
0145     IOCTL_READ_GGS = 13,
0146     IOCTL_WRITE_PGGS = 14,
0147     IOCTL_READ_PGGS = 15,
0148     /* Set healthy bit value */
0149     IOCTL_SET_BOOT_HEALTH_STATUS = 17,
0150     IOCTL_OSPI_MUX_SELECT = 21,
0151     /* Register SGI to ATF */
0152     IOCTL_REGISTER_SGI = 25,
0153     /* Runtime feature configuration */
0154     IOCTL_SET_FEATURE_CONFIG = 26,
0155     IOCTL_GET_FEATURE_CONFIG = 27,
0156 };
0157 
0158 enum pm_query_id {
0159     PM_QID_INVALID = 0,
0160     PM_QID_CLOCK_GET_NAME = 1,
0161     PM_QID_CLOCK_GET_TOPOLOGY = 2,
0162     PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS = 3,
0163     PM_QID_CLOCK_GET_PARENTS = 4,
0164     PM_QID_CLOCK_GET_ATTRIBUTES = 5,
0165     PM_QID_PINCTRL_GET_NUM_PINS = 6,
0166     PM_QID_PINCTRL_GET_NUM_FUNCTIONS = 7,
0167     PM_QID_PINCTRL_GET_NUM_FUNCTION_GROUPS = 8,
0168     PM_QID_PINCTRL_GET_FUNCTION_NAME = 9,
0169     PM_QID_PINCTRL_GET_FUNCTION_GROUPS = 10,
0170     PM_QID_PINCTRL_GET_PIN_GROUPS = 11,
0171     PM_QID_CLOCK_GET_NUM_CLOCKS = 12,
0172     PM_QID_CLOCK_GET_MAX_DIVISOR = 13,
0173 };
0174 
0175 enum zynqmp_pm_reset_action {
0176     PM_RESET_ACTION_RELEASE = 0,
0177     PM_RESET_ACTION_ASSERT = 1,
0178     PM_RESET_ACTION_PULSE = 2,
0179 };
0180 
0181 enum zynqmp_pm_reset {
0182     ZYNQMP_PM_RESET_START = 1000,
0183     ZYNQMP_PM_RESET_PCIE_CFG = ZYNQMP_PM_RESET_START,
0184     ZYNQMP_PM_RESET_PCIE_BRIDGE = 1001,
0185     ZYNQMP_PM_RESET_PCIE_CTRL = 1002,
0186     ZYNQMP_PM_RESET_DP = 1003,
0187     ZYNQMP_PM_RESET_SWDT_CRF = 1004,
0188     ZYNQMP_PM_RESET_AFI_FM5 = 1005,
0189     ZYNQMP_PM_RESET_AFI_FM4 = 1006,
0190     ZYNQMP_PM_RESET_AFI_FM3 = 1007,
0191     ZYNQMP_PM_RESET_AFI_FM2 = 1008,
0192     ZYNQMP_PM_RESET_AFI_FM1 = 1009,
0193     ZYNQMP_PM_RESET_AFI_FM0 = 1010,
0194     ZYNQMP_PM_RESET_GDMA = 1011,
0195     ZYNQMP_PM_RESET_GPU_PP1 = 1012,
0196     ZYNQMP_PM_RESET_GPU_PP0 = 1013,
0197     ZYNQMP_PM_RESET_GPU = 1014,
0198     ZYNQMP_PM_RESET_GT = 1015,
0199     ZYNQMP_PM_RESET_SATA = 1016,
0200     ZYNQMP_PM_RESET_ACPU3_PWRON = 1017,
0201     ZYNQMP_PM_RESET_ACPU2_PWRON = 1018,
0202     ZYNQMP_PM_RESET_ACPU1_PWRON = 1019,
0203     ZYNQMP_PM_RESET_ACPU0_PWRON = 1020,
0204     ZYNQMP_PM_RESET_APU_L2 = 1021,
0205     ZYNQMP_PM_RESET_ACPU3 = 1022,
0206     ZYNQMP_PM_RESET_ACPU2 = 1023,
0207     ZYNQMP_PM_RESET_ACPU1 = 1024,
0208     ZYNQMP_PM_RESET_ACPU0 = 1025,
0209     ZYNQMP_PM_RESET_DDR = 1026,
0210     ZYNQMP_PM_RESET_APM_FPD = 1027,
0211     ZYNQMP_PM_RESET_SOFT = 1028,
0212     ZYNQMP_PM_RESET_GEM0 = 1029,
0213     ZYNQMP_PM_RESET_GEM1 = 1030,
0214     ZYNQMP_PM_RESET_GEM2 = 1031,
0215     ZYNQMP_PM_RESET_GEM3 = 1032,
0216     ZYNQMP_PM_RESET_QSPI = 1033,
0217     ZYNQMP_PM_RESET_UART0 = 1034,
0218     ZYNQMP_PM_RESET_UART1 = 1035,
0219     ZYNQMP_PM_RESET_SPI0 = 1036,
0220     ZYNQMP_PM_RESET_SPI1 = 1037,
0221     ZYNQMP_PM_RESET_SDIO0 = 1038,
0222     ZYNQMP_PM_RESET_SDIO1 = 1039,
0223     ZYNQMP_PM_RESET_CAN0 = 1040,
0224     ZYNQMP_PM_RESET_CAN1 = 1041,
0225     ZYNQMP_PM_RESET_I2C0 = 1042,
0226     ZYNQMP_PM_RESET_I2C1 = 1043,
0227     ZYNQMP_PM_RESET_TTC0 = 1044,
0228     ZYNQMP_PM_RESET_TTC1 = 1045,
0229     ZYNQMP_PM_RESET_TTC2 = 1046,
0230     ZYNQMP_PM_RESET_TTC3 = 1047,
0231     ZYNQMP_PM_RESET_SWDT_CRL = 1048,
0232     ZYNQMP_PM_RESET_NAND = 1049,
0233     ZYNQMP_PM_RESET_ADMA = 1050,
0234     ZYNQMP_PM_RESET_GPIO = 1051,
0235     ZYNQMP_PM_RESET_IOU_CC = 1052,
0236     ZYNQMP_PM_RESET_TIMESTAMP = 1053,
0237     ZYNQMP_PM_RESET_RPU_R50 = 1054,
0238     ZYNQMP_PM_RESET_RPU_R51 = 1055,
0239     ZYNQMP_PM_RESET_RPU_AMBA = 1056,
0240     ZYNQMP_PM_RESET_OCM = 1057,
0241     ZYNQMP_PM_RESET_RPU_PGE = 1058,
0242     ZYNQMP_PM_RESET_USB0_CORERESET = 1059,
0243     ZYNQMP_PM_RESET_USB1_CORERESET = 1060,
0244     ZYNQMP_PM_RESET_USB0_HIBERRESET = 1061,
0245     ZYNQMP_PM_RESET_USB1_HIBERRESET = 1062,
0246     ZYNQMP_PM_RESET_USB0_APB = 1063,
0247     ZYNQMP_PM_RESET_USB1_APB = 1064,
0248     ZYNQMP_PM_RESET_IPI = 1065,
0249     ZYNQMP_PM_RESET_APM_LPD = 1066,
0250     ZYNQMP_PM_RESET_RTC = 1067,
0251     ZYNQMP_PM_RESET_SYSMON = 1068,
0252     ZYNQMP_PM_RESET_AFI_FM6 = 1069,
0253     ZYNQMP_PM_RESET_LPD_SWDT = 1070,
0254     ZYNQMP_PM_RESET_FPD = 1071,
0255     ZYNQMP_PM_RESET_RPU_DBG1 = 1072,
0256     ZYNQMP_PM_RESET_RPU_DBG0 = 1073,
0257     ZYNQMP_PM_RESET_DBG_LPD = 1074,
0258     ZYNQMP_PM_RESET_DBG_FPD = 1075,
0259     ZYNQMP_PM_RESET_APLL = 1076,
0260     ZYNQMP_PM_RESET_DPLL = 1077,
0261     ZYNQMP_PM_RESET_VPLL = 1078,
0262     ZYNQMP_PM_RESET_IOPLL = 1079,
0263     ZYNQMP_PM_RESET_RPLL = 1080,
0264     ZYNQMP_PM_RESET_GPO3_PL_0 = 1081,
0265     ZYNQMP_PM_RESET_GPO3_PL_1 = 1082,
0266     ZYNQMP_PM_RESET_GPO3_PL_2 = 1083,
0267     ZYNQMP_PM_RESET_GPO3_PL_3 = 1084,
0268     ZYNQMP_PM_RESET_GPO3_PL_4 = 1085,
0269     ZYNQMP_PM_RESET_GPO3_PL_5 = 1086,
0270     ZYNQMP_PM_RESET_GPO3_PL_6 = 1087,
0271     ZYNQMP_PM_RESET_GPO3_PL_7 = 1088,
0272     ZYNQMP_PM_RESET_GPO3_PL_8 = 1089,
0273     ZYNQMP_PM_RESET_GPO3_PL_9 = 1090,
0274     ZYNQMP_PM_RESET_GPO3_PL_10 = 1091,
0275     ZYNQMP_PM_RESET_GPO3_PL_11 = 1092,
0276     ZYNQMP_PM_RESET_GPO3_PL_12 = 1093,
0277     ZYNQMP_PM_RESET_GPO3_PL_13 = 1094,
0278     ZYNQMP_PM_RESET_GPO3_PL_14 = 1095,
0279     ZYNQMP_PM_RESET_GPO3_PL_15 = 1096,
0280     ZYNQMP_PM_RESET_GPO3_PL_16 = 1097,
0281     ZYNQMP_PM_RESET_GPO3_PL_17 = 1098,
0282     ZYNQMP_PM_RESET_GPO3_PL_18 = 1099,
0283     ZYNQMP_PM_RESET_GPO3_PL_19 = 1100,
0284     ZYNQMP_PM_RESET_GPO3_PL_20 = 1101,
0285     ZYNQMP_PM_RESET_GPO3_PL_21 = 1102,
0286     ZYNQMP_PM_RESET_GPO3_PL_22 = 1103,
0287     ZYNQMP_PM_RESET_GPO3_PL_23 = 1104,
0288     ZYNQMP_PM_RESET_GPO3_PL_24 = 1105,
0289     ZYNQMP_PM_RESET_GPO3_PL_25 = 1106,
0290     ZYNQMP_PM_RESET_GPO3_PL_26 = 1107,
0291     ZYNQMP_PM_RESET_GPO3_PL_27 = 1108,
0292     ZYNQMP_PM_RESET_GPO3_PL_28 = 1109,
0293     ZYNQMP_PM_RESET_GPO3_PL_29 = 1110,
0294     ZYNQMP_PM_RESET_GPO3_PL_30 = 1111,
0295     ZYNQMP_PM_RESET_GPO3_PL_31 = 1112,
0296     ZYNQMP_PM_RESET_RPU_LS = 1113,
0297     ZYNQMP_PM_RESET_PS_ONLY = 1114,
0298     ZYNQMP_PM_RESET_PL = 1115,
0299     ZYNQMP_PM_RESET_PS_PL0 = 1116,
0300     ZYNQMP_PM_RESET_PS_PL1 = 1117,
0301     ZYNQMP_PM_RESET_PS_PL2 = 1118,
0302     ZYNQMP_PM_RESET_PS_PL3 = 1119,
0303     ZYNQMP_PM_RESET_END = ZYNQMP_PM_RESET_PS_PL3
0304 };
0305 
0306 enum zynqmp_pm_suspend_reason {
0307     SUSPEND_POWER_REQUEST = 201,
0308     SUSPEND_ALERT = 202,
0309     SUSPEND_SYSTEM_SHUTDOWN = 203,
0310 };
0311 
0312 enum zynqmp_pm_request_ack {
0313     ZYNQMP_PM_REQUEST_ACK_NO = 1,
0314     ZYNQMP_PM_REQUEST_ACK_BLOCKING = 2,
0315     ZYNQMP_PM_REQUEST_ACK_NON_BLOCKING = 3,
0316 };
0317 
0318 enum pm_node_id {
0319     NODE_SD_0 = 39,
0320     NODE_SD_1 = 40,
0321 };
0322 
0323 enum tap_delay_type {
0324     PM_TAPDELAY_INPUT = 0,
0325     PM_TAPDELAY_OUTPUT = 1,
0326 };
0327 
0328 enum dll_reset_type {
0329     PM_DLL_RESET_ASSERT = 0,
0330     PM_DLL_RESET_RELEASE = 1,
0331     PM_DLL_RESET_PULSE = 2,
0332 };
0333 
0334 enum pm_pinctrl_config_param {
0335     PM_PINCTRL_CONFIG_SLEW_RATE = 0,
0336     PM_PINCTRL_CONFIG_BIAS_STATUS = 1,
0337     PM_PINCTRL_CONFIG_PULL_CTRL = 2,
0338     PM_PINCTRL_CONFIG_SCHMITT_CMOS = 3,
0339     PM_PINCTRL_CONFIG_DRIVE_STRENGTH = 4,
0340     PM_PINCTRL_CONFIG_VOLTAGE_STATUS = 5,
0341     PM_PINCTRL_CONFIG_TRI_STATE = 6,
0342     PM_PINCTRL_CONFIG_MAX = 7,
0343 };
0344 
0345 enum pm_pinctrl_slew_rate {
0346     PM_PINCTRL_SLEW_RATE_FAST = 0,
0347     PM_PINCTRL_SLEW_RATE_SLOW = 1,
0348 };
0349 
0350 enum pm_pinctrl_bias_status {
0351     PM_PINCTRL_BIAS_DISABLE = 0,
0352     PM_PINCTRL_BIAS_ENABLE = 1,
0353 };
0354 
0355 enum pm_pinctrl_pull_ctrl {
0356     PM_PINCTRL_BIAS_PULL_DOWN = 0,
0357     PM_PINCTRL_BIAS_PULL_UP = 1,
0358 };
0359 
0360 enum pm_pinctrl_schmitt_cmos {
0361     PM_PINCTRL_INPUT_TYPE_CMOS = 0,
0362     PM_PINCTRL_INPUT_TYPE_SCHMITT = 1,
0363 };
0364 
0365 enum pm_pinctrl_drive_strength {
0366     PM_PINCTRL_DRIVE_STRENGTH_2MA = 0,
0367     PM_PINCTRL_DRIVE_STRENGTH_4MA = 1,
0368     PM_PINCTRL_DRIVE_STRENGTH_8MA = 2,
0369     PM_PINCTRL_DRIVE_STRENGTH_12MA = 3,
0370 };
0371 
0372 enum pm_pinctrl_tri_state {
0373     PM_PINCTRL_TRI_STATE_DISABLE = 0,
0374     PM_PINCTRL_TRI_STATE_ENABLE = 1,
0375 };
0376 
0377 enum zynqmp_pm_shutdown_type {
0378     ZYNQMP_PM_SHUTDOWN_TYPE_SHUTDOWN = 0,
0379     ZYNQMP_PM_SHUTDOWN_TYPE_RESET = 1,
0380     ZYNQMP_PM_SHUTDOWN_TYPE_SETSCOPE_ONLY = 2,
0381 };
0382 
0383 enum zynqmp_pm_shutdown_subtype {
0384     ZYNQMP_PM_SHUTDOWN_SUBTYPE_SUBSYSTEM = 0,
0385     ZYNQMP_PM_SHUTDOWN_SUBTYPE_PS_ONLY = 1,
0386     ZYNQMP_PM_SHUTDOWN_SUBTYPE_SYSTEM = 2,
0387 };
0388 
0389 enum ospi_mux_select_type {
0390     PM_OSPI_MUX_SEL_DMA = 0,
0391     PM_OSPI_MUX_SEL_LINEAR = 1,
0392 };
0393 
0394 enum pm_feature_config_id {
0395     PM_FEATURE_INVALID = 0,
0396     PM_FEATURE_OVERTEMP_STATUS = 1,
0397     PM_FEATURE_OVERTEMP_VALUE = 2,
0398     PM_FEATURE_EXTWDT_STATUS = 3,
0399     PM_FEATURE_EXTWDT_VALUE = 4,
0400 };
0401 
0402 /**
0403  * struct zynqmp_pm_query_data - PM query data
0404  * @qid:    query ID
0405  * @arg1:   Argument 1 of query data
0406  * @arg2:   Argument 2 of query data
0407  * @arg3:   Argument 3 of query data
0408  */
0409 struct zynqmp_pm_query_data {
0410     u32 qid;
0411     u32 arg1;
0412     u32 arg2;
0413     u32 arg3;
0414 };
0415 
0416 int zynqmp_pm_invoke_fn(u32 pm_api_id, u32 arg0, u32 arg1,
0417             u32 arg2, u32 arg3, u32 *ret_payload);
0418 
0419 #if IS_REACHABLE(CONFIG_ZYNQMP_FIRMWARE)
0420 int zynqmp_pm_get_api_version(u32 *version);
0421 int zynqmp_pm_get_chipid(u32 *idcode, u32 *version);
0422 int zynqmp_pm_query_data(struct zynqmp_pm_query_data qdata, u32 *out);
0423 int zynqmp_pm_clock_enable(u32 clock_id);
0424 int zynqmp_pm_clock_disable(u32 clock_id);
0425 int zynqmp_pm_clock_getstate(u32 clock_id, u32 *state);
0426 int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider);
0427 int zynqmp_pm_clock_getdivider(u32 clock_id, u32 *divider);
0428 int zynqmp_pm_clock_setrate(u32 clock_id, u64 rate);
0429 int zynqmp_pm_clock_getrate(u32 clock_id, u64 *rate);
0430 int zynqmp_pm_clock_setparent(u32 clock_id, u32 parent_id);
0431 int zynqmp_pm_clock_getparent(u32 clock_id, u32 *parent_id);
0432 int zynqmp_pm_set_pll_frac_mode(u32 clk_id, u32 mode);
0433 int zynqmp_pm_get_pll_frac_mode(u32 clk_id, u32 *mode);
0434 int zynqmp_pm_set_pll_frac_data(u32 clk_id, u32 data);
0435 int zynqmp_pm_get_pll_frac_data(u32 clk_id, u32 *data);
0436 int zynqmp_pm_set_sd_tapdelay(u32 node_id, u32 type, u32 value);
0437 int zynqmp_pm_sd_dll_reset(u32 node_id, u32 type);
0438 int zynqmp_pm_ospi_mux_select(u32 dev_id, u32 select);
0439 int zynqmp_pm_reset_assert(const enum zynqmp_pm_reset reset,
0440                const enum zynqmp_pm_reset_action assert_flag);
0441 int zynqmp_pm_reset_get_status(const enum zynqmp_pm_reset reset, u32 *status);
0442 unsigned int zynqmp_pm_bootmode_read(u32 *ps_mode);
0443 int zynqmp_pm_bootmode_write(u32 ps_mode);
0444 int zynqmp_pm_init_finalize(void);
0445 int zynqmp_pm_set_suspend_mode(u32 mode);
0446 int zynqmp_pm_request_node(const u32 node, const u32 capabilities,
0447                const u32 qos, const enum zynqmp_pm_request_ack ack);
0448 int zynqmp_pm_release_node(const u32 node);
0449 int zynqmp_pm_set_requirement(const u32 node, const u32 capabilities,
0450                   const u32 qos,
0451                   const enum zynqmp_pm_request_ack ack);
0452 int zynqmp_pm_aes_engine(const u64 address, u32 *out);
0453 int zynqmp_pm_sha_hash(const u64 address, const u32 size, const u32 flags);
0454 int zynqmp_pm_fpga_load(const u64 address, const u32 size, const u32 flags);
0455 int zynqmp_pm_fpga_get_status(u32 *value);
0456 int zynqmp_pm_write_ggs(u32 index, u32 value);
0457 int zynqmp_pm_read_ggs(u32 index, u32 *value);
0458 int zynqmp_pm_write_pggs(u32 index, u32 value);
0459 int zynqmp_pm_read_pggs(u32 index, u32 *value);
0460 int zynqmp_pm_system_shutdown(const u32 type, const u32 subtype);
0461 int zynqmp_pm_set_boot_health_status(u32 value);
0462 int zynqmp_pm_pinctrl_request(const u32 pin);
0463 int zynqmp_pm_pinctrl_release(const u32 pin);
0464 int zynqmp_pm_pinctrl_get_function(const u32 pin, u32 *id);
0465 int zynqmp_pm_pinctrl_set_function(const u32 pin, const u32 id);
0466 int zynqmp_pm_pinctrl_get_config(const u32 pin, const u32 param,
0467                  u32 *value);
0468 int zynqmp_pm_pinctrl_set_config(const u32 pin, const u32 param,
0469                  u32 value);
0470 int zynqmp_pm_load_pdi(const u32 src, const u64 address);
0471 int zynqmp_pm_register_notifier(const u32 node, const u32 event,
0472                 const u32 wake, const u32 enable);
0473 int zynqmp_pm_feature(const u32 api_id);
0474 int zynqmp_pm_is_function_supported(const u32 api_id, const u32 id);
0475 int zynqmp_pm_set_feature_config(enum pm_feature_config_id id, u32 value);
0476 int zynqmp_pm_get_feature_config(enum pm_feature_config_id id, u32 *payload);
0477 int zynqmp_pm_register_sgi(u32 sgi_num, u32 reset);
0478 #else
0479 static inline int zynqmp_pm_get_api_version(u32 *version)
0480 {
0481     return -ENODEV;
0482 }
0483 
0484 static inline int zynqmp_pm_get_chipid(u32 *idcode, u32 *version)
0485 {
0486     return -ENODEV;
0487 }
0488 
0489 static inline int zynqmp_pm_query_data(struct zynqmp_pm_query_data qdata,
0490                        u32 *out)
0491 {
0492     return -ENODEV;
0493 }
0494 
0495 static inline int zynqmp_pm_clock_enable(u32 clock_id)
0496 {
0497     return -ENODEV;
0498 }
0499 
0500 static inline int zynqmp_pm_clock_disable(u32 clock_id)
0501 {
0502     return -ENODEV;
0503 }
0504 
0505 static inline int zynqmp_pm_clock_getstate(u32 clock_id, u32 *state)
0506 {
0507     return -ENODEV;
0508 }
0509 
0510 static inline int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider)
0511 {
0512     return -ENODEV;
0513 }
0514 
0515 static inline int zynqmp_pm_clock_getdivider(u32 clock_id, u32 *divider)
0516 {
0517     return -ENODEV;
0518 }
0519 
0520 static inline int zynqmp_pm_clock_setrate(u32 clock_id, u64 rate)
0521 {
0522     return -ENODEV;
0523 }
0524 
0525 static inline int zynqmp_pm_clock_getrate(u32 clock_id, u64 *rate)
0526 {
0527     return -ENODEV;
0528 }
0529 
0530 static inline int zynqmp_pm_clock_setparent(u32 clock_id, u32 parent_id)
0531 {
0532     return -ENODEV;
0533 }
0534 
0535 static inline int zynqmp_pm_clock_getparent(u32 clock_id, u32 *parent_id)
0536 {
0537     return -ENODEV;
0538 }
0539 
0540 static inline int zynqmp_pm_set_pll_frac_mode(u32 clk_id, u32 mode)
0541 {
0542     return -ENODEV;
0543 }
0544 
0545 static inline int zynqmp_pm_get_pll_frac_mode(u32 clk_id, u32 *mode)
0546 {
0547     return -ENODEV;
0548 }
0549 
0550 static inline int zynqmp_pm_set_pll_frac_data(u32 clk_id, u32 data)
0551 {
0552     return -ENODEV;
0553 }
0554 
0555 static inline int zynqmp_pm_get_pll_frac_data(u32 clk_id, u32 *data)
0556 {
0557     return -ENODEV;
0558 }
0559 
0560 static inline int zynqmp_pm_set_sd_tapdelay(u32 node_id, u32 type, u32 value)
0561 {
0562     return -ENODEV;
0563 }
0564 
0565 static inline int zynqmp_pm_sd_dll_reset(u32 node_id, u32 type)
0566 {
0567     return -ENODEV;
0568 }
0569 
0570 static inline int zynqmp_pm_ospi_mux_select(u32 dev_id, u32 select)
0571 {
0572     return -ENODEV;
0573 }
0574 
0575 static inline int zynqmp_pm_reset_assert(const enum zynqmp_pm_reset reset,
0576                      const enum zynqmp_pm_reset_action assert_flag)
0577 {
0578     return -ENODEV;
0579 }
0580 
0581 static inline int zynqmp_pm_reset_get_status(const enum zynqmp_pm_reset reset,
0582                          u32 *status)
0583 {
0584     return -ENODEV;
0585 }
0586 
0587 static inline unsigned int zynqmp_pm_bootmode_read(u32 *ps_mode)
0588 {
0589     return -ENODEV;
0590 }
0591 
0592 static inline int zynqmp_pm_bootmode_write(u32 ps_mode)
0593 {
0594     return -ENODEV;
0595 }
0596 
0597 static inline int zynqmp_pm_init_finalize(void)
0598 {
0599     return -ENODEV;
0600 }
0601 
0602 static inline int zynqmp_pm_set_suspend_mode(u32 mode)
0603 {
0604     return -ENODEV;
0605 }
0606 
0607 static inline int zynqmp_pm_request_node(const u32 node, const u32 capabilities,
0608                      const u32 qos,
0609                      const enum zynqmp_pm_request_ack ack)
0610 {
0611     return -ENODEV;
0612 }
0613 
0614 static inline int zynqmp_pm_release_node(const u32 node)
0615 {
0616     return -ENODEV;
0617 }
0618 
0619 static inline int zynqmp_pm_set_requirement(const u32 node,
0620                         const u32 capabilities,
0621                         const u32 qos,
0622                         const enum zynqmp_pm_request_ack ack)
0623 {
0624     return -ENODEV;
0625 }
0626 
0627 static inline int zynqmp_pm_aes_engine(const u64 address, u32 *out)
0628 {
0629     return -ENODEV;
0630 }
0631 
0632 static inline int zynqmp_pm_sha_hash(const u64 address, const u32 size,
0633                      const u32 flags)
0634 {
0635     return -ENODEV;
0636 }
0637 
0638 static inline int zynqmp_pm_fpga_load(const u64 address, const u32 size,
0639                       const u32 flags)
0640 {
0641     return -ENODEV;
0642 }
0643 
0644 static inline int zynqmp_pm_fpga_get_status(u32 *value)
0645 {
0646     return -ENODEV;
0647 }
0648 
0649 static inline int zynqmp_pm_write_ggs(u32 index, u32 value)
0650 {
0651     return -ENODEV;
0652 }
0653 
0654 static inline int zynqmp_pm_read_ggs(u32 index, u32 *value)
0655 {
0656     return -ENODEV;
0657 }
0658 
0659 static inline int zynqmp_pm_write_pggs(u32 index, u32 value)
0660 {
0661     return -ENODEV;
0662 }
0663 
0664 static inline int zynqmp_pm_read_pggs(u32 index, u32 *value)
0665 {
0666     return -ENODEV;
0667 }
0668 
0669 static inline int zynqmp_pm_system_shutdown(const u32 type, const u32 subtype)
0670 {
0671     return -ENODEV;
0672 }
0673 
0674 static inline int zynqmp_pm_set_boot_health_status(u32 value)
0675 {
0676     return -ENODEV;
0677 }
0678 
0679 static inline int zynqmp_pm_pinctrl_request(const u32 pin)
0680 {
0681     return -ENODEV;
0682 }
0683 
0684 static inline int zynqmp_pm_pinctrl_release(const u32 pin)
0685 {
0686     return -ENODEV;
0687 }
0688 
0689 static inline int zynqmp_pm_pinctrl_get_function(const u32 pin, u32 *id)
0690 {
0691     return -ENODEV;
0692 }
0693 
0694 static inline int zynqmp_pm_is_function_supported(const u32 api_id, const u32 id)
0695 {
0696     return -ENODEV;
0697 }
0698 
0699 static inline int zynqmp_pm_pinctrl_set_function(const u32 pin, const u32 id)
0700 {
0701     return -ENODEV;
0702 }
0703 
0704 static inline int zynqmp_pm_pinctrl_get_config(const u32 pin, const u32 param,
0705                            u32 *value)
0706 {
0707     return -ENODEV;
0708 }
0709 
0710 static inline int zynqmp_pm_pinctrl_set_config(const u32 pin, const u32 param,
0711                            u32 value)
0712 {
0713     return -ENODEV;
0714 }
0715 
0716 static inline int zynqmp_pm_load_pdi(const u32 src, const u64 address)
0717 {
0718     return -ENODEV;
0719 }
0720 
0721 static inline int zynqmp_pm_register_notifier(const u32 node, const u32 event,
0722                           const u32 wake, const u32 enable)
0723 {
0724     return -ENODEV;
0725 }
0726 
0727 static inline int zynqmp_pm_feature(const u32 api_id)
0728 {
0729     return -ENODEV;
0730 }
0731 
0732 static inline int zynqmp_pm_set_feature_config(enum pm_feature_config_id id,
0733                            u32 value)
0734 {
0735     return -ENODEV;
0736 }
0737 
0738 static inline int zynqmp_pm_get_feature_config(enum pm_feature_config_id id,
0739                            u32 *payload)
0740 {
0741     return -ENODEV;
0742 }
0743 
0744 static inline int zynqmp_pm_register_sgi(u32 sgi_num, u32 reset)
0745 {
0746     return -ENODEV;
0747 }
0748 #endif
0749 
0750 #endif /* __FIRMWARE_ZYNQMP_H__ */
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!